llvm/lib/CodeGen
Evan Cheng 0a942dbb1e Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:08:17 +00:00
..
AsmPrinter Do not forget to mark prcessed arguments. 2010-05-14 21:55:50 +00:00
PBQP
SelectionDAG Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 2010-05-19 01:08:17 +00:00
AggressiveAntiDepBreaker.cpp Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
AggressiveAntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
Analysis.cpp Move several SelectionDAG-independent utility functions out of the 2010-04-21 01:22:34 +00:00
AntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
BranchFolding.cpp Fix a bug which prevented tail merging of return instructions in 2010-05-03 14:35:47 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CMakeLists.txt Add fast register allocator, enabled with -regalloc=fast. 2010-04-21 18:02:42 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Remove trailing whitespace 2010-05-14 21:20:46 +00:00
CriticalAntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp Code that needs a TargetMachine should have access to one directly, rather 2010-04-19 19:05:59 +00:00
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
ELFWriter.h Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
ExactHazardRecognizer.cpp Initial support for different kinds of FU reservation. 2010-04-07 18:19:32 +00:00
ExactHazardRecognizer.h Initial support for different kinds of FU reservation. 2010-04-07 18:19:32 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp mcize the gc metadata printing stuff. 2010-04-04 07:39:04 +00:00
GCStrategy.cpp Revert 101465, it broke internal OpenGL testing. 2010-04-16 23:37:20 +00:00
IfConversion.cpp
IntrinsicLowering.cpp Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 2010-05-11 06:17:44 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Introduce SpecificBumpPtrAllocator, a wrapper for BumpPtrAllocator which allows 2010-03-30 20:16:45 +00:00
LiveIntervalAnalysis.cpp Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy. 2010-05-17 01:47:47 +00:00
LiveStackAnalysis.cpp Introduce SpecificBumpPtrAllocator, a wrapper for BumpPtrAllocator which allows 2010-03-30 20:16:45 +00:00
LiveVariables.cpp Eliminate MachineBasicBlock::const_livein_iterator and make 2010-04-13 16:57:55 +00:00
LLVMTargetMachine.cpp llc (et al): Add support for --show-encoding and --show-inst. 2010-05-18 17:22:19 +00:00
LowerSubregs.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
MachineBasicBlock.cpp Eliminate MachineBasicBlock::const_livein_iterator and make 2010-04-13 16:57:55 +00:00
MachineCSE.cpp Add a utility function for conservatively clearing kill flags, and make 2010-05-13 19:24:00 +00:00
MachineDominators.cpp
MachineFunction.cpp Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
MachineFunctionAnalysis.cpp Start function numbering at 0. 2010-04-17 16:29:15 +00:00
MachineFunctionPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineFunctionPrinterPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineInstr.cpp Teach MachineLICM and MachineSink how to clear kill flags conservatively 2010-05-13 20:34:42 +00:00
MachineLICM.cpp Teach MachineLICM and MachineSink how to clear kill flags conservatively 2010-05-13 20:34:42 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp The JIT calls TidyLandingPads to tidy up the landing pads. However, because the 2010-04-16 08:46:10 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Add a utility function for conservatively clearing kill flags, and make 2010-05-13 19:24:00 +00:00
MachineSink.cpp Teach MachineLICM and MachineSink how to clear kill flags conservatively 2010-05-13 20:34:42 +00:00
MachineSSAUpdater.cpp Fix PR7096. When a block containing multiple defs is tail duplicated, the 2010-05-10 17:14:26 +00:00
MachineVerifier.cpp Teach the machine code verifier to use getSubRegisterRegClass(). 2010-05-18 17:31:12 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp Handle DEBUG_VALUE in this pass. 2010-03-26 00:02:44 +00:00
OptimizePHIs.cpp
Passes.cpp
PHIElimination.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
PHIElimination.h Move REG_SEQUENCE removal to 2addr pass. 2010-05-05 18:45:40 +00:00
PostRASchedulerList.cpp 80 column and trailing whitespace cleanup 2010-05-14 21:19:48 +00:00
PreAllocSplitting.cpp Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 2010-05-06 19:06:44 +00:00
ProcessImplicitDefs.cpp It's not safe eliminate copies where src and dst have different sub-register indices. 2010-05-11 00:20:03 +00:00
PrologEpilogInserter.cpp Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 2010-05-14 21:14:32 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocFast.cpp Properly handle multiple definitions of a virtual register in the same 2010-05-18 21:10:50 +00:00
RegAllocLinearScan.cpp improve portability to systems that don't have powf/modf (e.g. solaris 9) 2010-05-15 17:10:24 +00:00
RegAllocLocal.cpp Remember to update VirtRegLastUse when spilling without killing before a call. 2010-05-18 22:20:09 +00:00
RegAllocPBQP.cpp improve portability to systems that don't have powf/modf (e.g. solaris 9) 2010-05-15 17:10:24 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 2010-05-06 19:06:44 +00:00
ScheduleDAG.cpp Remove unused member variable. 2010-05-17 09:47:55 +00:00
ScheduleDAGEmit.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
ScheduleDAGInstrs.cpp Get rid of the EdgeMapping map. Instead, just check for BasicBlock 2010-05-01 00:01:06 +00:00
ScheduleDAGInstrs.h I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 2010-05-11 20:16:09 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp use abstract accessors to CallInst 2010-04-20 13:13:04 +00:00
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp Fix a crash when debugging the coalescer. DebugValue instructions are not 2010-05-18 23:19:42 +00:00
SimpleRegisterCoalescing.h Slightly verboser debug spew from coalescer 2010-04-29 22:21:48 +00:00
SjLjEHPrepare.cpp Revert 101465, it broke internal OpenGL testing. 2010-04-16 23:37:20 +00:00
SlotIndexes.cpp
Spiller.cpp Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 2010-05-11 06:17:44 +00:00
Spiller.h
StackProtector.cpp
StackSlotColoring.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
StrongPHIElimination.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
TailDuplication.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
TargetInstrInfoImpl.cpp rename llvm::llvm_report_error -> llvm::report_fatal_error 2010-04-07 22:58:41 +00:00
TargetLoweringObjectFileImpl.cpp More data/parsing support for tls directives. Add a few more testcases 2010-05-17 22:53:55 +00:00
TwoAddressInstructionPass.cpp Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions. 2010-05-17 23:24:12 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp It's not safe eliminate copies where src and dst have different sub-register indices. 2010-05-11 00:20:03 +00:00
VirtRegRewriter.h Code clean up. Move includes from VirtRegRewriter.h to VirtRegRewriter.cpp. 2010-04-06 17:19:55 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.