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38caf19333
Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277624 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1.2 KiB
LLVM
25 lines
1.2 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
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define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
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%tmp = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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%tmp3 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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%tmp4 = fmul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4, <4 x float>* %P3
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store <4 x float> zeroinitializer, <4 x float>* %P1
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store <4 x i32> zeroinitializer, <4 x i32>* %P2
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ret void
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}
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; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
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; to vmaddfp (so it would IEEE compliant with zero sign propagation).
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; CHECK: @VXOR
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; CHECK: vsplti
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; CHECK: vxor
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define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
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store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
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store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3
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ret void
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}
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; CHECK: @VSPLTI
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; CHECK: vsplti
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