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LLVM PR/29052 highlighted that FastISel for MIPS attempted to lower arguments assuming that it was using the paired 32bit registers to perform operations for f64. This mode of operation is not supported for MIPSR6. This patch resolves the reported issue by adding additional checks for unsupported floating point unit configuration. Thanks to mike.k for reporting this issue! Reviewers: seanbruno, vkalintiris Differential Review: https://reviews.llvm.org/D23795 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280706 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
434 B
LLVM
15 lines
434 B
LLVM
; RUN: not llc -march=mipsel -mcpu=mips32r2 -fast-isel -mattr=+fp64 < %s \
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; RUN: -fast-isel-abort=3
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; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
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; supports AFGR64 only, which uses paired 32 bit registers.
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define zeroext i1 @f(double %value) {
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entry:
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; CHECK-LABEL: f:
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; CHECK: sdc1
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%value.addr = alloca double, align 8
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store double %value, double* %value.addr, align 8
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ret i1 false
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}
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