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ad58f8c997
Summary: dst_sel and dst_unused disabled for VOPC as they have no effect on result Reviewers: artem.tamazov, tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21376 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274340 91177308-0d34-0410-b5e6-96231b3b80d8
298 lines
6.7 KiB
TableGen
298 lines
6.7 KiB
TableGen
//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// VI Instruction format definitions.
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//
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//===----------------------------------------------------------------------===//
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class DSe_vi <bits<8> op> : Enc64 {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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bits<8> data0;
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bits<8> data1;
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bits<8> offset0;
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bits<8> offset1;
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let Inst{7-0} = offset0;
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let Inst{15-8} = offset1;
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let Inst{16} = gds;
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let Inst{24-17} = op;
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let Inst{31-26} = 0x36; //encoding
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let Inst{39-32} = addr;
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let Inst{47-40} = data0;
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let Inst{55-48} = data1;
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let Inst{63-56} = vdst;
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}
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class MUBUFe_vi <bits<7> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<1> lds;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{16} = lds;
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let Inst{17} = slc;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x38; //encoding
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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}
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class MTBUFe_vi <bits<4> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<4> dfmt;
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bits<3> nfmt;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{18-15} = op;
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let Inst{22-19} = dfmt;
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let Inst{25-23} = nfmt;
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let Inst{31-26} = 0x3a; //encoding
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{54} = slc;
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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}
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class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
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bits<7> sbase;
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bits<7> sdst;
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bits<1> glc;
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let Inst{5-0} = sbase{6-1};
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let Inst{12-6} = sdst;
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let Inst{16} = glc;
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let Inst{17} = imm;
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let Inst{25-18} = op;
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let Inst{31-26} = 0x30; //encoding
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}
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class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> {
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bits<20> offset;
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let Inst{51-32} = offset;
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}
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class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> {
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bits<20> soff;
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let Inst{51-32} = soff;
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}
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class VOP3a_vi <bits<10> op> : Enc64 {
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<1> clamp;
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bits<2> omod;
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let Inst{8} = src0_modifiers{1};
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let Inst{9} = src1_modifiers{1};
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let Inst{10} = src2_modifiers{1};
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let Inst{15} = clamp;
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let Inst{25-16} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{61} = src0_modifiers{0};
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let Inst{62} = src1_modifiers{0};
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let Inst{63} = src2_modifiers{0};
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}
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class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
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bits<8> vdst;
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let Inst{7-0} = vdst;
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}
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// Encoding used for VOPC instructions encoded as VOP3
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// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
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class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
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bits<8> sdst;
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let Inst{7-0} = sdst;
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}
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class VOP3be_vi <bits<10> op> : Enc64 {
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bits<8> vdst;
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<7> sdst;
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bits<2> omod;
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bits<1> clamp;
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let Inst{7-0} = vdst;
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let Inst{14-8} = sdst;
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let Inst{15} = clamp;
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let Inst{25-16} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{61} = src0_modifiers{0};
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let Inst{62} = src1_modifiers{0};
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let Inst{63} = src2_modifiers{0};
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}
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class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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let DPP = 1;
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let Size = 8;
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let AsmMatchConverter = !if(!eq(HasMods,1), "cvtDPP", "");
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}
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class VOP_DPPe : Enc64 {
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bits<2> src0_modifiers;
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bits<8> src0;
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bits<2> src1_modifiers;
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bits<9> dpp_ctrl;
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bits<1> bound_ctrl;
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bits<4> bank_mask;
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bits<4> row_mask;
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let Inst{39-32} = src0;
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let Inst{48-40} = dpp_ctrl;
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let Inst{51} = bound_ctrl;
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let Inst{52} = src0_modifiers{0}; // src0_neg
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let Inst{53} = src0_modifiers{1}; // src0_abs
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let Inst{54} = src1_modifiers{0}; // src1_neg
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let Inst{55} = src1_modifiers{1}; // src1_abs
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let Inst{59-56} = bank_mask;
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let Inst{63-60} = row_mask;
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}
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class VOP1_DPPe <bits<8> op> : VOP_DPPe {
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bits<8> vdst;
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let Inst{8-0} = 0xfa; // dpp
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let Inst{16-9} = op;
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let Inst{24-17} = vdst;
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let Inst{31-25} = 0x3f; //encoding
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}
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class VOP2_DPPe <bits<6> op> : VOP_DPPe {
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bits<8> vdst;
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bits<8> src1;
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let Inst{8-0} = 0xfa; //dpp
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let Inst{16-9} = src1;
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let Inst{24-17} = vdst;
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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}
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class VOP_SDWA <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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let SDWA = 1;
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let Size = 8;
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}
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class VOP_SDWAe : Enc64 {
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bits<8> src0;
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bits<3> src0_sel;
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bits<2> src0_fmodifiers; // {abs,neg}
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bits<1> src0_imodifiers; // sext
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bits<3> src1_sel;
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bits<2> src1_fmodifiers;
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bits<1> src1_imodifiers;
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bits<3> dst_sel;
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bits<2> dst_unused;
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bits<1> clamp;
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let Inst{39-32} = src0;
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let Inst{42-40} = dst_sel;
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let Inst{44-43} = dst_unused;
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let Inst{45} = clamp;
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let Inst{50-48} = src0_sel;
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let Inst{53-52} = src0_fmodifiers;
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let Inst{51} = src0_imodifiers;
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let Inst{58-56} = src1_sel;
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let Inst{61-60} = src1_fmodifiers;
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let Inst{59} = src1_imodifiers;
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}
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class VOP1_SDWAe <bits<8> op> : VOP_SDWAe {
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bits<8> vdst;
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let Inst{8-0} = 0xf9; // sdwa
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let Inst{16-9} = op;
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let Inst{24-17} = vdst;
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let Inst{31-25} = 0x3f; // encoding
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}
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class VOP2_SDWAe <bits<6> op> : VOP_SDWAe {
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bits<8> vdst;
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bits<8> src1;
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let Inst{8-0} = 0xf9; // sdwa
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let Inst{16-9} = src1;
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let Inst{24-17} = vdst;
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let Inst{30-25} = op;
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let Inst{31} = 0x0; // encoding
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}
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class VOPC_SDWAe <bits<8> op> : VOP_SDWAe {
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bits<8> src1;
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let Inst{8-0} = 0xf9; // sdwa
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let Inst{16-9} = src1;
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let Inst{24-17} = op;
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let Inst{31-25} = 0x3e; // encoding
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// VOPC disallows dst_sel and dst_unused as they have no effect on destination
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let Inst{42-40} = 0x6;
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let Inst{44-43} = 0x2;
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}
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class EXPe_vi : EXPe {
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let Inst{31-26} = 0x31; //encoding
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}
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class VINTRPe_vi <bits<2> op> : VINTRPe <op> {
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let Inst{31-26} = 0x35; // encoding
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}
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