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4784f1fc73
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
1127 lines
39 KiB
C++
1127 lines
39 KiB
C++
//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Methods common to all machine instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Constants.h"
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#include "llvm/InlineAsm.h"
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#include "llvm/Value.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrDesc.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/Support/LeakDetector.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Streams.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/FoldingSet.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// MachineOperand Implementation
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//===----------------------------------------------------------------------===//
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/// AddRegOperandToRegInfo - Add this register operand to the specified
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/// MachineRegisterInfo. If it is null, then the next/prev fields should be
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/// explicitly nulled out.
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void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
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assert(isReg() && "Can only add reg operand to use lists");
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// If the reginfo pointer is null, just explicitly null out or next/prev
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// pointers, to ensure they are not garbage.
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if (RegInfo == 0) {
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Contents.Reg.Prev = 0;
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Contents.Reg.Next = 0;
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return;
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}
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// Otherwise, add this operand to the head of the registers use/def list.
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MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
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// For SSA values, we prefer to keep the definition at the start of the list.
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// we do this by skipping over the definition if it is at the head of the
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// list.
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if (*Head && (*Head)->isDef())
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Head = &(*Head)->Contents.Reg.Next;
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Contents.Reg.Next = *Head;
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if (Contents.Reg.Next) {
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assert(getReg() == Contents.Reg.Next->getReg() &&
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"Different regs on the same list!");
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Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
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}
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Contents.Reg.Prev = Head;
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*Head = this;
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}
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/// RemoveRegOperandFromRegInfo - Remove this register operand from the
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/// MachineRegisterInfo it is linked with.
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void MachineOperand::RemoveRegOperandFromRegInfo() {
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assert(isOnRegUseList() && "Reg operand is not on a use list");
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// Unlink this from the doubly linked list of operands.
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MachineOperand *NextOp = Contents.Reg.Next;
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*Contents.Reg.Prev = NextOp;
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if (NextOp) {
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assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
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NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
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}
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Contents.Reg.Prev = 0;
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Contents.Reg.Next = 0;
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}
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void MachineOperand::setReg(unsigned Reg) {
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if (getReg() == Reg) return; // No change.
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// Otherwise, we have to change the register. If this operand is embedded
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// into a machine function, we need to update the old and new register's
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// use/def lists.
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if (MachineInstr *MI = getParent())
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if (MachineBasicBlock *MBB = MI->getParent())
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if (MachineFunction *MF = MBB->getParent()) {
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RemoveRegOperandFromRegInfo();
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Contents.Reg.RegNo = Reg;
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AddRegOperandToRegInfo(&MF->getRegInfo());
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return;
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}
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// Otherwise, just change the register, no problem. :)
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Contents.Reg.RegNo = Reg;
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}
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/// ChangeToImmediate - Replace this operand with a new immediate operand of
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/// the specified value. If an operand is known to be an immediate already,
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/// the setImm method should be used.
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void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
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// If this operand is currently a register operand, and if this is in a
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// function, deregister the operand from the register's use/def list.
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if (isReg() && getParent() && getParent()->getParent() &&
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getParent()->getParent()->getParent())
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RemoveRegOperandFromRegInfo();
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OpKind = MO_Immediate;
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Contents.ImmVal = ImmVal;
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}
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/// ChangeToRegister - Replace this operand with a new register operand of
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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bool isKill, bool isDead, bool isUndef) {
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// If this operand is already a register operand, use setReg to update the
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// register's use/def lists.
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if (isReg()) {
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assert(!isEarlyClobber());
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setReg(Reg);
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} else {
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// Otherwise, change this to a register and set the reg#.
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OpKind = MO_Register;
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Contents.Reg.RegNo = Reg;
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// If this operand is embedded in a function, add the operand to the
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// register's use/def list.
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if (MachineInstr *MI = getParent())
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if (MachineBasicBlock *MBB = MI->getParent())
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if (MachineFunction *MF = MBB->getParent())
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AddRegOperandToRegInfo(&MF->getRegInfo());
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}
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IsDef = isDef;
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IsImp = isImp;
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IsKill = isKill;
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IsDead = isDead;
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IsUndef = isUndef;
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IsEarlyClobber = false;
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SubReg = 0;
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}
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/// isIdenticalTo - Return true if this operand is identical to the specified
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/// operand.
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bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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if (getType() != Other.getType() ||
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getTargetFlags() != Other.getTargetFlags())
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return false;
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switch (getType()) {
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default: assert(0 && "Unrecognized operand type");
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case MachineOperand::MO_Register:
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return getReg() == Other.getReg() && isDef() == Other.isDef() &&
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getSubReg() == Other.getSubReg();
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case MachineOperand::MO_Immediate:
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return getImm() == Other.getImm();
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case MachineOperand::MO_FPImmediate:
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return getFPImm() == Other.getFPImm();
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case MachineOperand::MO_MachineBasicBlock:
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return getMBB() == Other.getMBB();
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case MachineOperand::MO_FrameIndex:
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return getIndex() == Other.getIndex();
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case MachineOperand::MO_ConstantPoolIndex:
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return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
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case MachineOperand::MO_JumpTableIndex:
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return getIndex() == Other.getIndex();
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case MachineOperand::MO_GlobalAddress:
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return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
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case MachineOperand::MO_ExternalSymbol:
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return !strcmp(getSymbolName(), Other.getSymbolName()) &&
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getOffset() == Other.getOffset();
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}
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}
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/// print - Print the specified machine operand.
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///
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void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
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raw_os_ostream RawOS(OS);
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print(RawOS, TM);
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}
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void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
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switch (getType()) {
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case MachineOperand::MO_Register:
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if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
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OS << "%reg" << getReg();
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} else {
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// If the instruction is embedded into a basic block, we can find the
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// target info for the instruction.
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if (TM == 0)
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if (const MachineInstr *MI = getParent())
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if (const MachineBasicBlock *MBB = MI->getParent())
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if (const MachineFunction *MF = MBB->getParent())
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TM = &MF->getTarget();
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if (TM)
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OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
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else
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OS << "%mreg" << getReg();
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}
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if (getSubReg() != 0)
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OS << ':' << getSubReg();
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if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
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isEarlyClobber()) {
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OS << '<';
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bool NeedComma = false;
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if (isImplicit()) {
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if (NeedComma) OS << ',';
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OS << (isDef() ? "imp-def" : "imp-use");
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NeedComma = true;
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} else if (isDef()) {
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if (NeedComma) OS << ',';
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if (isEarlyClobber())
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OS << "earlyclobber,";
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OS << "def";
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NeedComma = true;
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}
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if (isKill() || isDead() || isUndef()) {
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if (NeedComma) OS << ',';
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if (isKill()) OS << "kill";
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if (isDead()) OS << "dead";
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if (isUndef()) {
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if (isKill() || isDead())
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OS << ',';
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OS << "undef";
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}
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}
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OS << '>';
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}
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break;
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case MachineOperand::MO_Immediate:
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OS << getImm();
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break;
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case MachineOperand::MO_FPImmediate:
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if (getFPImm()->getType() == Type::FloatTy)
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OS << getFPImm()->getValueAPF().convertToFloat();
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else
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OS << getFPImm()->getValueAPF().convertToDouble();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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OS << "mbb<"
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<< ((Value*)getMBB()->getBasicBlock())->getName()
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<< "," << (void*)getMBB() << '>';
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << getIndex() << '>';
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << getIndex();
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if (getOffset()) OS << "+" << getOffset();
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OS << '>';
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break;
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case MachineOperand::MO_JumpTableIndex:
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OS << "<jt#" << getIndex() << '>';
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)getGlobal())->getName();
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if (getOffset()) OS << "+" << getOffset();
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OS << '>';
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << getSymbolName();
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if (getOffset()) OS << "+" << getOffset();
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OS << '>';
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break;
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default:
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assert(0 && "Unrecognized operand type");
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}
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if (unsigned TF = getTargetFlags())
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OS << "[TF=" << TF << ']';
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}
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//===----------------------------------------------------------------------===//
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// MachineMemOperand Implementation
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//===----------------------------------------------------------------------===//
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MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
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int64_t o, uint64_t s, unsigned int a)
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: Offset(o), Size(s), V(v),
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Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
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assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
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assert((isLoad() || isStore()) && "Not a load/store!");
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}
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/// Profile - Gather unique data for the object.
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///
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void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
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ID.AddInteger(Offset);
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ID.AddInteger(Size);
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ID.AddPointer(V);
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ID.AddInteger(Flags);
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}
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//===----------------------------------------------------------------------===//
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// MachineInstr Implementation
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//===----------------------------------------------------------------------===//
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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/// TID NULL and no operands.
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MachineInstr::MachineInstr()
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: TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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void MachineInstr::addImplicitDefUseOperands() {
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
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}
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDesc or the numOperands if it is not zero. (for
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/// instructions with variable number of operands).
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MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
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: TID(&tid), NumImplicitOps(0), Parent(0),
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debugLoc(DebugLoc::getUnknownLoc()) {
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if (!NoImp && TID->getImplicitDefs())
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for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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if (!NoImp && TID->getImplicitUses())
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for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID->getNumOperands());
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if (!NoImp)
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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/// MachineInstr ctor - As above, but with a DebugLoc.
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MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
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bool NoImp)
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: TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
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if (!NoImp && TID->getImplicitDefs())
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for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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if (!NoImp && TID->getImplicitUses())
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for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID->getNumOperands());
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if (!NoImp)
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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/// MachineInstr ctor - Work exactly the same as the ctor two above, except
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/// that the MachineInstr is created and added to the end of the specified
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/// basic block.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
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: TID(&tid), NumImplicitOps(0), Parent(0),
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debugLoc(DebugLoc::getUnknownLoc()) {
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID->getNumOperands());
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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/// MachineInstr ctor - As above, but with a DebugLoc.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
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const TargetInstrDesc &tid)
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: TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
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NumImplicitOps++;
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
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NumImplicitOps++;
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Operands.reserve(NumImplicitOps + TID->getNumOperands());
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addImplicitDefUseOperands();
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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///
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MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
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: TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
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debugLoc(MI.getDebugLoc()) {
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Operands.reserve(MI.getNumOperands());
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// Add operands
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for (unsigned i = 0; i != MI.getNumOperands(); ++i)
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addOperand(MI.getOperand(i));
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NumImplicitOps = MI.NumImplicitOps;
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// Add memory operands.
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for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
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j = MI.memoperands_end(); i != j; ++i)
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addMemOperand(MF, *i);
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// Set parent to null.
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Parent = 0;
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LeakDetector::addGarbageObject(this);
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}
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MachineInstr::~MachineInstr() {
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LeakDetector::removeGarbageObject(this);
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assert(MemOperands.empty() &&
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"MachineInstr being deleted with live memoperands!");
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#ifndef NDEBUG
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
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assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
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"Reg operand def/use list corrupted");
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}
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#endif
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}
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/// getRegInfo - If this instruction is embedded into a MachineFunction,
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/// return the MachineRegisterInfo object for the current function, otherwise
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/// return null.
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MachineRegisterInfo *MachineInstr::getRegInfo() {
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if (MachineBasicBlock *MBB = getParent())
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return &MBB->getParent()->getRegInfo();
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return 0;
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}
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/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
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/// this instruction from their respective use lists. This requires that the
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/// operands already be on their use lists.
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void MachineInstr::RemoveRegOperandsFromUseLists() {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i].isReg())
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Operands[i].RemoveRegOperandFromRegInfo();
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}
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}
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/// AddRegOperandsToUseLists - Add all of the register operands in
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/// this instruction from their respective use lists. This requires that the
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/// operands not be on their use lists yet.
|
|
void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
|
|
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
|
|
if (Operands[i].isReg())
|
|
Operands[i].AddRegOperandToRegInfo(&RegInfo);
|
|
}
|
|
}
|
|
|
|
|
|
/// addOperand - Add the specified operand to the instruction. If it is an
|
|
/// implicit operand, it is added to the end of the operand list. If it is
|
|
/// an explicit operand it is added at the end of the explicit operand list
|
|
/// (before the first implicit operand).
|
|
void MachineInstr::addOperand(const MachineOperand &Op) {
|
|
bool isImpReg = Op.isReg() && Op.isImplicit();
|
|
assert((isImpReg || !OperandsComplete()) &&
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
MachineRegisterInfo *RegInfo = getRegInfo();
|
|
|
|
// If we are adding the operand to the end of the list, our job is simpler.
|
|
// This is true most of the time, so this is a reasonable optimization.
|
|
if (isImpReg || NumImplicitOps == 0) {
|
|
// We can only do this optimization if we know that the operand list won't
|
|
// reallocate.
|
|
if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
|
|
Operands.push_back(Op);
|
|
|
|
// Set the parent of the operand.
|
|
Operands.back().ParentMI = this;
|
|
|
|
// If the operand is a register, update the operand's use list.
|
|
if (Op.isReg())
|
|
Operands.back().AddRegOperandToRegInfo(RegInfo);
|
|
return;
|
|
}
|
|
}
|
|
|
|
// Otherwise, we have to insert a real operand before any implicit ones.
|
|
unsigned OpNo = Operands.size()-NumImplicitOps;
|
|
|
|
// If this instruction isn't embedded into a function, then we don't need to
|
|
// update any operand lists.
|
|
if (RegInfo == 0) {
|
|
// Simple insertion, no reginfo update needed for other register operands.
|
|
Operands.insert(Operands.begin()+OpNo, Op);
|
|
Operands[OpNo].ParentMI = this;
|
|
|
|
// Do explicitly set the reginfo for this operand though, to ensure the
|
|
// next/prev fields are properly nulled out.
|
|
if (Operands[OpNo].isReg())
|
|
Operands[OpNo].AddRegOperandToRegInfo(0);
|
|
|
|
} else if (Operands.size()+1 <= Operands.capacity()) {
|
|
// Otherwise, we have to remove register operands from their register use
|
|
// list, add the operand, then add the register operands back to their use
|
|
// list. This also must handle the case when the operand list reallocates
|
|
// to somewhere else.
|
|
|
|
// If insertion of this operand won't cause reallocation of the operand
|
|
// list, just remove the implicit operands, add the operand, then re-add all
|
|
// the rest of the operands.
|
|
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
|
|
assert(Operands[i].isReg() && "Should only be an implicit reg!");
|
|
Operands[i].RemoveRegOperandFromRegInfo();
|
|
}
|
|
|
|
// Add the operand. If it is a register, add it to the reg list.
|
|
Operands.insert(Operands.begin()+OpNo, Op);
|
|
Operands[OpNo].ParentMI = this;
|
|
|
|
if (Operands[OpNo].isReg())
|
|
Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
|
|
|
|
// Re-add all the implicit ops.
|
|
for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
|
|
assert(Operands[i].isReg() && "Should only be an implicit reg!");
|
|
Operands[i].AddRegOperandToRegInfo(RegInfo);
|
|
}
|
|
} else {
|
|
// Otherwise, we will be reallocating the operand list. Remove all reg
|
|
// operands from their list, then readd them after the operand list is
|
|
// reallocated.
|
|
RemoveRegOperandsFromUseLists();
|
|
|
|
Operands.insert(Operands.begin()+OpNo, Op);
|
|
Operands[OpNo].ParentMI = this;
|
|
|
|
// Re-add all the operands.
|
|
AddRegOperandsToUseLists(*RegInfo);
|
|
}
|
|
}
|
|
|
|
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
|
|
/// fewer operand than it started with.
|
|
///
|
|
void MachineInstr::RemoveOperand(unsigned OpNo) {
|
|
assert(OpNo < Operands.size() && "Invalid operand number");
|
|
|
|
// Special case removing the last one.
|
|
if (OpNo == Operands.size()-1) {
|
|
// If needed, remove from the reg def/use list.
|
|
if (Operands.back().isReg() && Operands.back().isOnRegUseList())
|
|
Operands.back().RemoveRegOperandFromRegInfo();
|
|
|
|
Operands.pop_back();
|
|
return;
|
|
}
|
|
|
|
// Otherwise, we are removing an interior operand. If we have reginfo to
|
|
// update, remove all operands that will be shifted down from their reg lists,
|
|
// move everything down, then re-add them.
|
|
MachineRegisterInfo *RegInfo = getRegInfo();
|
|
if (RegInfo) {
|
|
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
|
|
if (Operands[i].isReg())
|
|
Operands[i].RemoveRegOperandFromRegInfo();
|
|
}
|
|
}
|
|
|
|
Operands.erase(Operands.begin()+OpNo);
|
|
|
|
if (RegInfo) {
|
|
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
|
|
if (Operands[i].isReg())
|
|
Operands[i].AddRegOperandToRegInfo(RegInfo);
|
|
}
|
|
}
|
|
}
|
|
|
|
/// addMemOperand - Add a MachineMemOperand to the machine instruction,
|
|
/// referencing arbitrary storage.
|
|
void MachineInstr::addMemOperand(MachineFunction &MF,
|
|
const MachineMemOperand &MO) {
|
|
MemOperands.push_back(MO);
|
|
}
|
|
|
|
/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
|
|
void MachineInstr::clearMemOperands(MachineFunction &MF) {
|
|
MemOperands.clear();
|
|
}
|
|
|
|
|
|
/// removeFromParent - This method unlinks 'this' from the containing basic
|
|
/// block, and returns it, but does not delete it.
|
|
MachineInstr *MachineInstr::removeFromParent() {
|
|
assert(getParent() && "Not embedded in a basic block!");
|
|
getParent()->remove(this);
|
|
return this;
|
|
}
|
|
|
|
|
|
/// eraseFromParent - This method unlinks 'this' from the containing basic
|
|
/// block, and deletes it.
|
|
void MachineInstr::eraseFromParent() {
|
|
assert(getParent() && "Not embedded in a basic block!");
|
|
getParent()->erase(this);
|
|
}
|
|
|
|
|
|
/// OperandComplete - Return true if it's illegal to add a new operand
|
|
///
|
|
bool MachineInstr::OperandsComplete() const {
|
|
unsigned short NumOperands = TID->getNumOperands();
|
|
if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
|
|
return true; // Broken: we have all the operands of this instruction!
|
|
return false;
|
|
}
|
|
|
|
/// getNumExplicitOperands - Returns the number of non-implicit operands.
|
|
///
|
|
unsigned MachineInstr::getNumExplicitOperands() const {
|
|
unsigned NumOperands = TID->getNumOperands();
|
|
if (!TID->isVariadic())
|
|
return NumOperands;
|
|
|
|
for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = getOperand(i);
|
|
if (!MO.isReg() || !MO.isImplicit())
|
|
NumOperands++;
|
|
}
|
|
return NumOperands;
|
|
}
|
|
|
|
|
|
/// isLabel - Returns true if the MachineInstr represents a label.
|
|
///
|
|
bool MachineInstr::isLabel() const {
|
|
return getOpcode() == TargetInstrInfo::DBG_LABEL ||
|
|
getOpcode() == TargetInstrInfo::EH_LABEL ||
|
|
getOpcode() == TargetInstrInfo::GC_LABEL;
|
|
}
|
|
|
|
/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
|
|
///
|
|
bool MachineInstr::isDebugLabel() const {
|
|
return getOpcode() == TargetInstrInfo::DBG_LABEL;
|
|
}
|
|
|
|
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
|
|
/// the specific register or -1 if it is not found. It further tightening
|
|
/// the search criteria to a use that kills the register if isKill is true.
|
|
int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
|
|
const TargetRegisterInfo *TRI) const {
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (!MOReg)
|
|
continue;
|
|
if (MOReg == Reg ||
|
|
(TRI &&
|
|
TargetRegisterInfo::isPhysicalRegister(MOReg) &&
|
|
TargetRegisterInfo::isPhysicalRegister(Reg) &&
|
|
TRI->isSubRegister(MOReg, Reg)))
|
|
if (!isKill || MO.isKill())
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
|
|
/// the specified register or -1 if it is not found. If isDead is true, defs
|
|
/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
|
|
/// also checks if there is a def of a super-register.
|
|
int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
|
|
const TargetRegisterInfo *TRI) const {
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (MOReg == Reg ||
|
|
(TRI &&
|
|
TargetRegisterInfo::isPhysicalRegister(MOReg) &&
|
|
TargetRegisterInfo::isPhysicalRegister(Reg) &&
|
|
TRI->isSubRegister(MOReg, Reg)))
|
|
if (!isDead || MO.isDead())
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
/// findFirstPredOperandIdx() - Find the index of the first operand in the
|
|
/// operand list that is used to represent the predicate. It returns -1 if
|
|
/// none is found.
|
|
int MachineInstr::findFirstPredOperandIdx() const {
|
|
const TargetInstrDesc &TID = getDesc();
|
|
if (TID.isPredicable()) {
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
|
if (TID.OpInfo[i].isPredicate())
|
|
return i;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
/// isRegTiedToUseOperand - Given the index of a register def operand,
|
|
/// check if the register def is tied to a source operand, due to either
|
|
/// two-address elimination or inline assembly constraints. Returns the
|
|
/// first tied use operand index by reference is UseOpIdx is not null.
|
|
bool MachineInstr::
|
|
isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
|
|
if (getOpcode() == TargetInstrInfo::INLINEASM) {
|
|
assert(DefOpIdx >= 2);
|
|
const MachineOperand &MO = getOperand(DefOpIdx);
|
|
if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
|
|
return false;
|
|
// Determine the actual operand index that corresponds to this index.
|
|
unsigned DefNo = 0;
|
|
unsigned DefPart = 0;
|
|
for (unsigned i = 1, e = getNumOperands(); i < e; ) {
|
|
const MachineOperand &FMO = getOperand(i);
|
|
assert(FMO.isImm());
|
|
// Skip over this def.
|
|
unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
|
|
unsigned PrevDef = i + 1;
|
|
i = PrevDef + NumOps;
|
|
if (i > DefOpIdx) {
|
|
DefPart = DefOpIdx - PrevDef;
|
|
break;
|
|
}
|
|
++DefNo;
|
|
}
|
|
for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &FMO = getOperand(i);
|
|
if (!FMO.isImm())
|
|
continue;
|
|
if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
|
|
continue;
|
|
unsigned Idx;
|
|
if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
|
|
Idx == DefNo) {
|
|
if (UseOpIdx)
|
|
*UseOpIdx = (unsigned)i + 1 + DefPart;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
|
|
const TargetInstrDesc &TID = getDesc();
|
|
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = getOperand(i);
|
|
if (MO.isReg() && MO.isUse() &&
|
|
TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
|
|
if (UseOpIdx)
|
|
*UseOpIdx = (unsigned)i;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// isRegTiedToDefOperand - Return true if the operand of the specified index
|
|
/// is a register use and it is tied to an def operand. It also returns the def
|
|
/// operand index by reference.
|
|
bool MachineInstr::
|
|
isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
|
|
if (getOpcode() == TargetInstrInfo::INLINEASM) {
|
|
const MachineOperand &MO = getOperand(UseOpIdx);
|
|
if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
|
|
return false;
|
|
int FlagIdx = UseOpIdx - 1;
|
|
if (FlagIdx < 1)
|
|
return false;
|
|
while (!getOperand(FlagIdx).isImm()) {
|
|
if (--FlagIdx == 0)
|
|
return false;
|
|
}
|
|
const MachineOperand &UFMO = getOperand(FlagIdx);
|
|
if (FlagIdx + InlineAsm::getNumOperandRegisters(UFMO.getImm()) < UseOpIdx)
|
|
return false;
|
|
unsigned DefNo;
|
|
if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
|
|
if (!DefOpIdx)
|
|
return true;
|
|
|
|
unsigned DefIdx = 1;
|
|
// Remember to adjust the index. First operand is asm string, then there
|
|
// is a flag for each.
|
|
while (DefNo) {
|
|
const MachineOperand &FMO = getOperand(DefIdx);
|
|
assert(FMO.isImm());
|
|
// Skip over this def.
|
|
DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
|
|
--DefNo;
|
|
}
|
|
*DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
const TargetInstrDesc &TID = getDesc();
|
|
if (UseOpIdx >= TID.getNumOperands())
|
|
return false;
|
|
const MachineOperand &MO = getOperand(UseOpIdx);
|
|
if (!MO.isReg() || !MO.isUse())
|
|
return false;
|
|
int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
|
|
if (DefIdx == -1)
|
|
return false;
|
|
if (DefOpIdx)
|
|
*DefOpIdx = (unsigned)DefIdx;
|
|
return true;
|
|
}
|
|
|
|
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
|
|
///
|
|
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
|
|
continue;
|
|
for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
|
|
MachineOperand &MOp = getOperand(j);
|
|
if (!MOp.isIdenticalTo(MO))
|
|
continue;
|
|
if (MO.isKill())
|
|
MOp.setIsKill();
|
|
else
|
|
MOp.setIsDead();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// copyPredicates - Copies predicate operand(s) from MI.
|
|
void MachineInstr::copyPredicates(const MachineInstr *MI) {
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
if (!TID.isPredicable())
|
|
return;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
if (TID.OpInfo[i].isPredicate()) {
|
|
// Predicated operands must be last operands.
|
|
addOperand(MI->getOperand(i));
|
|
}
|
|
}
|
|
}
|
|
|
|
/// isSafeToMove - Return true if it is safe to move this instruction. If
|
|
/// SawStore is set to true, it means that there is a store (or call) between
|
|
/// the instruction's location and its intended destination.
|
|
bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
|
|
bool &SawStore) const {
|
|
// Ignore stuff that we obviously can't move.
|
|
if (TID->mayStore() || TID->isCall()) {
|
|
SawStore = true;
|
|
return false;
|
|
}
|
|
if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
|
|
return false;
|
|
|
|
// See if this instruction does a load. If so, we have to guarantee that the
|
|
// loaded value doesn't change between the load and the its intended
|
|
// destination. The check for isInvariantLoad gives the targe the chance to
|
|
// classify the load as always returning a constant, e.g. a constant pool
|
|
// load.
|
|
if (TID->mayLoad() && !TII->isInvariantLoad(this))
|
|
// Otherwise, this is a real load. If there is a store between the load and
|
|
// end of block, or if the laod is volatile, we can't move it.
|
|
return !SawStore && !hasVolatileMemoryRef();
|
|
|
|
return true;
|
|
}
|
|
|
|
/// isSafeToReMat - Return true if it's safe to rematerialize the specified
|
|
/// instruction which defined the specified register instead of copying it.
|
|
bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
|
|
unsigned DstReg) const {
|
|
bool SawStore = false;
|
|
if (!getDesc().isRematerializable() ||
|
|
!TII->isTriviallyReMaterializable(this) ||
|
|
!isSafeToMove(TII, SawStore))
|
|
return false;
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
// FIXME: For now, do not remat any instruction with register operands.
|
|
// Later on, we can loosen the restriction is the register operands have
|
|
// not been modified between the def and use. Note, this is different from
|
|
// MachineSink because the code is no longer in two-address form (at least
|
|
// partially).
|
|
if (MO.isUse())
|
|
return false;
|
|
else if (!MO.isDead() && MO.getReg() != DstReg)
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// hasVolatileMemoryRef - Return true if this instruction may have a
|
|
/// volatile memory reference, or if the information describing the
|
|
/// memory reference is not available. Return false if it is known to
|
|
/// have no volatile memory references.
|
|
bool MachineInstr::hasVolatileMemoryRef() const {
|
|
// An instruction known never to access memory won't have a volatile access.
|
|
if (!TID->mayStore() &&
|
|
!TID->mayLoad() &&
|
|
!TID->isCall() &&
|
|
!TID->hasUnmodeledSideEffects())
|
|
return false;
|
|
|
|
// Otherwise, if the instruction has no memory reference information,
|
|
// conservatively assume it wasn't preserved.
|
|
if (memoperands_empty())
|
|
return true;
|
|
|
|
// Check the memory reference information for volatile references.
|
|
for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
|
|
E = memoperands_end(); I != E; ++I)
|
|
if (I->isVolatile())
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
void MachineInstr::dump() const {
|
|
cerr << " " << *this;
|
|
}
|
|
|
|
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
|
|
raw_os_ostream RawOS(OS);
|
|
print(RawOS, TM);
|
|
}
|
|
|
|
void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
|
|
// Specialize printing if op#0 is definition
|
|
unsigned StartOp = 0;
|
|
if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
|
|
getOperand(0).print(OS, TM);
|
|
OS << " = ";
|
|
++StartOp; // Don't print this operand again!
|
|
}
|
|
|
|
OS << getDesc().getName();
|
|
|
|
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
|
|
if (i != StartOp)
|
|
OS << ",";
|
|
OS << " ";
|
|
getOperand(i).print(OS, TM);
|
|
}
|
|
|
|
if (!memoperands_empty()) {
|
|
OS << ", Mem:";
|
|
for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
|
|
e = memoperands_end(); i != e; ++i) {
|
|
const MachineMemOperand &MRO = *i;
|
|
const Value *V = MRO.getValue();
|
|
|
|
assert((MRO.isLoad() || MRO.isStore()) &&
|
|
"SV has to be a load, store or both.");
|
|
|
|
if (MRO.isVolatile())
|
|
OS << "Volatile ";
|
|
|
|
if (MRO.isLoad())
|
|
OS << "LD";
|
|
if (MRO.isStore())
|
|
OS << "ST";
|
|
|
|
OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
|
|
|
|
if (!V)
|
|
OS << "<unknown>";
|
|
else if (!V->getName().empty())
|
|
OS << V->getName();
|
|
else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
|
|
PSV->print(OS);
|
|
} else
|
|
OS << V;
|
|
|
|
OS << " + " << MRO.getOffset() << "]";
|
|
}
|
|
}
|
|
|
|
if (!debugLoc.isUnknown()) {
|
|
const MachineFunction *MF = getParent()->getParent();
|
|
DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
|
|
DICompileUnit CU(DLT.CompileUnit);
|
|
std::string Dir, Fn;
|
|
OS << " [dbg: "
|
|
<< CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
|
|
<< DLT.Line << ","
|
|
<< DLT.Col << "]";
|
|
}
|
|
|
|
OS << "\n";
|
|
}
|
|
|
|
bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
|
|
const TargetRegisterInfo *RegInfo,
|
|
bool AddIfNotFound) {
|
|
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
|
|
bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
|
|
bool Found = false;
|
|
SmallVector<unsigned,4> DeadOps;
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!Reg)
|
|
continue;
|
|
|
|
if (Reg == IncomingReg) {
|
|
if (!Found) {
|
|
if (MO.isKill())
|
|
// The register is already marked kill.
|
|
return true;
|
|
MO.setIsKill();
|
|
Found = true;
|
|
}
|
|
} else if (hasAliases && MO.isKill() &&
|
|
TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
// A super-register kill already exists.
|
|
if (RegInfo->isSuperRegister(IncomingReg, Reg))
|
|
return true;
|
|
if (RegInfo->isSubRegister(IncomingReg, Reg))
|
|
DeadOps.push_back(i);
|
|
}
|
|
}
|
|
|
|
// Trim unneeded kill operands.
|
|
while (!DeadOps.empty()) {
|
|
unsigned OpIdx = DeadOps.back();
|
|
if (getOperand(OpIdx).isImplicit())
|
|
RemoveOperand(OpIdx);
|
|
else
|
|
getOperand(OpIdx).setIsKill(false);
|
|
DeadOps.pop_back();
|
|
}
|
|
|
|
// If not found, this means an alias of one of the operands is killed. Add a
|
|
// new implicit operand if required.
|
|
if (!Found && AddIfNotFound) {
|
|
addOperand(MachineOperand::CreateReg(IncomingReg,
|
|
false /*IsDef*/,
|
|
true /*IsImp*/,
|
|
true /*IsKill*/));
|
|
return true;
|
|
}
|
|
return Found;
|
|
}
|
|
|
|
bool MachineInstr::addRegisterDead(unsigned IncomingReg,
|
|
const TargetRegisterInfo *RegInfo,
|
|
bool AddIfNotFound) {
|
|
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
|
|
bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
|
|
bool Found = false;
|
|
SmallVector<unsigned,4> DeadOps;
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!Reg)
|
|
continue;
|
|
|
|
if (Reg == IncomingReg) {
|
|
if (!Found) {
|
|
if (MO.isDead())
|
|
// The register is already marked dead.
|
|
return true;
|
|
MO.setIsDead();
|
|
Found = true;
|
|
}
|
|
} else if (hasAliases && MO.isDead() &&
|
|
TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
// There exists a super-register that's marked dead.
|
|
if (RegInfo->isSuperRegister(IncomingReg, Reg))
|
|
return true;
|
|
if (RegInfo->getSubRegisters(IncomingReg) &&
|
|
RegInfo->getSuperRegisters(Reg) &&
|
|
RegInfo->isSubRegister(IncomingReg, Reg))
|
|
DeadOps.push_back(i);
|
|
}
|
|
}
|
|
|
|
// Trim unneeded dead operands.
|
|
while (!DeadOps.empty()) {
|
|
unsigned OpIdx = DeadOps.back();
|
|
if (getOperand(OpIdx).isImplicit())
|
|
RemoveOperand(OpIdx);
|
|
else
|
|
getOperand(OpIdx).setIsDead(false);
|
|
DeadOps.pop_back();
|
|
}
|
|
|
|
// If not found, this means an alias of one of the operands is dead. Add a
|
|
// new implicit operand if required.
|
|
if (Found || !AddIfNotFound)
|
|
return Found;
|
|
|
|
addOperand(MachineOperand::CreateReg(IncomingReg,
|
|
true /*IsDef*/,
|
|
true /*IsImp*/,
|
|
false /*IsKill*/,
|
|
true /*IsDead*/));
|
|
return true;
|
|
}
|