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eb92f5a745
This is the same change on PPC64 as r255821 on AArch64. I have even borrowed his commit message. The access function has a short entry and a short exit, the initialization block is only run the first time. To improve the performance, we want to have a short frame at the entry and exit. We explicitly handle most of the CSRs via copies. Only the CSRs that are not handled via copies will be in CSR_SaveList. Frame lowering and prologue/epilogue insertion will generate a short frame in the entry and exit according to CSR_SaveList. The majority of the CSRs will be handled by register allcoator. Register allocator will try to spill and reload them in the initialization block. We add CSRsViaCopy, it will be explicitly handled during lowering. 1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target supports it for the given machine function and the function has only return exits). We also call TLI->initializeSplitCSR to perform initialization. 2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to virtual registers at beginning of the entry block and copies from virtual registers to CSRsViaCopy at beginning of the exit blocks. 3> we also need to make sure the explicit copies will not be eliminated. Author: Tom Jablin (tjablin) Reviewers: hfinkel kbarton cycheng http://reviews.llvm.org/D17533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265781 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
7.7 KiB
C++
218 lines
7.7 KiB
C++
//===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of MachineFunctionInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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/// PPCFunctionInfo - This class is derived from MachineFunction private
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/// PowerPC target-specific information for each MachineFunction.
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class PPCFunctionInfo : public MachineFunctionInfo {
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virtual void anchor();
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/// FramePointerSaveIndex - Frame index of where the old frame pointer is
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/// stored. Also used as an anchor for instructions that need to be altered
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/// when using frame pointers (dyna_add, dyna_sub.)
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int FramePointerSaveIndex;
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/// ReturnAddrSaveIndex - Frame index of where the return address is stored.
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///
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int ReturnAddrSaveIndex;
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/// Frame index where the old base pointer is stored.
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int BasePointerSaveIndex;
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/// Frame index where the old PIC base pointer is stored.
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int PICBasePointerSaveIndex;
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/// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
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/// function. This is only valid after the initial scan of the function by
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/// PEI.
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bool MustSaveLR;
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/// Does this function have any stack spills.
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bool HasSpills;
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/// Does this function spill using instructions with only r+r (not r+i)
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/// forms.
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bool HasNonRISpills;
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/// SpillsCR - Indicates whether CR is spilled in the current function.
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bool SpillsCR;
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/// Indicates whether VRSAVE is spilled in the current function.
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bool SpillsVRSAVE;
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/// LRStoreRequired - The bool indicates whether there is some explicit use of
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/// the LR/LR8 stack slot that is not obvious from scanning the code. This
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/// requires that the code generator produce a store of LR to the stack on
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/// entry, even though LR may otherwise apparently not be used.
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bool LRStoreRequired;
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/// This function makes use of the PPC64 ELF TOC base pointer (register r2).
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bool UsesTOCBasePtr;
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/// MinReservedArea - This is the frame size that is at least reserved in a
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/// potential caller (parameter+linkage area).
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unsigned MinReservedArea;
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/// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum
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/// amount the stack pointer is adjusted to make the frame bigger for tail
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/// calls. Used for creating an area before the register spill area.
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int TailCallSPDelta;
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/// HasFastCall - Does this function contain a fast call. Used to determine
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/// how the caller's stack pointer should be calculated (epilog/dynamicalloc).
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bool HasFastCall;
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/// VarArgsFrameIndex - FrameIndex for start of varargs area.
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int VarArgsFrameIndex;
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/// VarArgsStackOffset - StackOffset for start of stack
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/// arguments.
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int VarArgsStackOffset;
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/// VarArgsNumGPR - Index of the first unused integer
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/// register for parameter passing.
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unsigned VarArgsNumGPR;
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/// VarArgsNumFPR - Index of the first unused double
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/// register for parameter passing.
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unsigned VarArgsNumFPR;
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/// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
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int CRSpillFrameIndex;
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/// If any of CR[2-4] need to be saved in the prologue and restored in the
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/// epilogue then they are added to this array. This is used for the
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/// 64-bit SVR4 ABI.
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SmallVector<unsigned, 3> MustSaveCRs;
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/// Hold onto our MachineFunction context.
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MachineFunction &MF;
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/// Whether this uses the PIC Base register or not.
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bool UsesPICBase;
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/// True if this function has a subset of CSRs that is handled explicitly via
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/// copies
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bool IsSplitCSR;
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public:
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explicit PPCFunctionInfo(MachineFunction &MF)
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: FramePointerSaveIndex(0),
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ReturnAddrSaveIndex(0),
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BasePointerSaveIndex(0),
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PICBasePointerSaveIndex(0),
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HasSpills(false),
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HasNonRISpills(false),
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SpillsCR(false),
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SpillsVRSAVE(false),
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LRStoreRequired(false),
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UsesTOCBasePtr(false),
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MinReservedArea(0),
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TailCallSPDelta(0),
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HasFastCall(false),
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VarArgsFrameIndex(0),
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VarArgsStackOffset(0),
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VarArgsNumGPR(0),
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VarArgsNumFPR(0),
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CRSpillFrameIndex(0),
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MF(MF),
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UsesPICBase(0),
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IsSplitCSR(false) {}
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int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
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void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
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int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
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void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
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int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
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void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }
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int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; }
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void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; }
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unsigned getMinReservedArea() const { return MinReservedArea; }
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void setMinReservedArea(unsigned size) { MinReservedArea = size; }
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int getTailCallSPDelta() const { return TailCallSPDelta; }
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void setTailCallSPDelta(int size) { TailCallSPDelta = size; }
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/// MustSaveLR - This is set when the prolog/epilog inserter does its initial
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/// scan of the function. It is true if the LR/LR8 register is ever explicitly
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/// defined/clobbered in the machine function (e.g. by calls and movpctolr,
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/// which is used in PIC generation), or if the LR stack slot is explicitly
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/// referenced by builtin_return_address.
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void setMustSaveLR(bool U) { MustSaveLR = U; }
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bool mustSaveLR() const { return MustSaveLR; }
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void setHasSpills() { HasSpills = true; }
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bool hasSpills() const { return HasSpills; }
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void setHasNonRISpills() { HasNonRISpills = true; }
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bool hasNonRISpills() const { return HasNonRISpills; }
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void setSpillsCR() { SpillsCR = true; }
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bool isCRSpilled() const { return SpillsCR; }
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void setSpillsVRSAVE() { SpillsVRSAVE = true; }
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bool isVRSAVESpilled() const { return SpillsVRSAVE; }
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void setLRStoreRequired() { LRStoreRequired = true; }
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bool isLRStoreRequired() const { return LRStoreRequired; }
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void setUsesTOCBasePtr() { UsesTOCBasePtr = true; }
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bool usesTOCBasePtr() const { return UsesTOCBasePtr; }
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void setHasFastCall() { HasFastCall = true; }
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bool hasFastCall() const { return HasFastCall;}
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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int getVarArgsStackOffset() const { return VarArgsStackOffset; }
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void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
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unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
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void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
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unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
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void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
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int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
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void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
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const SmallVectorImpl<unsigned> &
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getMustSaveCRs() const { return MustSaveCRs; }
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void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
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void setUsesPICBase(bool uses) { UsesPICBase = uses; }
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bool usesPICBase() const { return UsesPICBase; }
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bool isSplitCSR() const { return IsSplitCSR; }
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void setIsSplitCSR(bool s) { IsSplitCSR = s; }
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MCSymbol *getPICOffsetSymbol() const;
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MCSymbol *getGlobalEPSymbol() const;
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MCSymbol *getLocalEPSymbol() const;
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MCSymbol *getTOCOffsetSymbol() const;
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};
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} // end of namespace llvm
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#endif
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