Jakob Stoklund Olesen 864c8702ba Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:

  (add (zext cc), x) -> (select cc (add x, 1), x)
  (add (sext cc), x) -> (select cc (add x, -1), x)

For a function like:

  unsigned f(unsigned s, int x) {
    return s + (x>0);
  }

We now produce:

  cmp r1, #0
  it  gt
  addgt.w r0, r0, #1

Instead of:

  movs  r2, #0
  cmp r1, #0
  it  gt
  movgt r2, #1
  add r0, r2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:22 +00:00
2012-07-19 00:23:13 +00:00
2012-08-08 18:04:45 +00:00
2012-07-23 08:51:15 +00:00
2012-05-02 21:25:32 +00:00
2012-08-15 22:35:36 +00:00
2012-08-14 18:14:22 +00:00
2012-06-19 23:47:58 +00:00
2012-04-03 23:09:22 +00:00
2012-07-11 17:34:12 +00:00

Low Level Virtual Machine (LLVM)
================================

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