llvm/test/CodeGen/Mips/delay-slot-kill.ll
Vasileios Kalintiris edcaae782e Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
It introduced two regressions on 64-bit big-endian targets running under N32
(MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets
comparisons such as BEQ compare the whole GPR64 but incorrectly tell the
instruction selector that they operate on GPR32's. This leads to the
elimination of i32->i64 extensions that are actually required by
comparisons to work correctly.

There's currently a patch under review that fixes this problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243984 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-04 14:26:35 +00:00

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LLVM

; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
; We have to XFAIL this temporarily because of the reversion of r229675.
; XFAIL: *
; Currently, the following IR assembly generates a KILL instruction between
; the bitwise-and instruction and the return instruction. We verify that the
; delay slot filler ignores such KILL instructions by filling the slot of the
; return instruction properly.
define signext i32 @f1(i32 signext %a, i32 signext %b) {
entry:
; CHECK: jr $ra
; CHECK-NEXT: and $2, $4, $5
%r = and i32 %a, %b
ret i32 %r
}