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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
2.4 KiB
LLVM
70 lines
2.4 KiB
LLVM
; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s
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; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s
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; RUN: llc -march=ppc32 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s
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; RUN: llc -march=ppc32 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s
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target triple = "powerpc64-unknown-linux-gnu"
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; Test correct assembly code generation for thread-local storage using
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; the local dynamic model.
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@a = hidden thread_local global i32 0, align 4
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define signext i32 @main() nounwind {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32, i32* @a, align 4
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ret i32 %0
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}
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; OPT0-LABEL: main:
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; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
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; OPT0: addi 3, [[REG]], a@got@tlsld@l
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; OPT0: bl __tls_get_addr(a@tlsld)
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; OPT0-NEXT: nop
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; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
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; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
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; OPT0-32-LABEL: main
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; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld
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; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT
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; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha
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; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l
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; OPT1-32-LABEL: main
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; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld
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; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT
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; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha
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; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l
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; Test peephole optimization for thread-local storage using the
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; local dynamic model.
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; OPT1-LABEL: main:
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; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
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; OPT1: addi 3, [[REG]], a@got@tlsld@l
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; OPT1: bl __tls_get_addr(a@tlsld)
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; OPT1-NEXT: nop
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; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
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; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
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; Test correct assembly code generation for thread-local storage using
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; the general dynamic model.
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@a2 = thread_local global i32 0, align 4
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define signext i32 @main2() nounwind {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32, i32* @a2, align 4
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ret i32 %0
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}
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; OPT1-LABEL: main2
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; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha
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; OPT1: addi 3, [[REG]], a2@got@tlsgd@l
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; OPT1: bl __tls_get_addr(a2@tlsgd)
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; OPT1-NEXT: nop
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; OPT1-32-LABEL: main2
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; OPT1-32: addi 3, {{[0-9]+}}, a2@got@tlsgd
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; OPT1-32: bl __tls_get_addr(a2@tlsgd)@PLT
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