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8afb08e5b5
Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209421 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
1.8 KiB
LLVM
65 lines
1.8 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s
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define i32 @main() nounwind {
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entry:
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; First I with short
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; CHECK: #APP
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; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096
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; CHECK: #NO_APP
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tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
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; Then I with int
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; CHECK: #APP
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; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
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; Now J with 0
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; CHECK: #APP
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; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
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; Now K with 64
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; CHECK: #APP
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; CHECK: addu ${{[0-9]+}},${{[0-9]+}},64
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; CHECK: #NO_APP
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tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
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; Now L with 0x00100000
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; CHECK: #APP
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; CHECK: add ${{[0-9]+}},${{[0-9]+}},${{[0-9]+}}
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
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; Now N with -3
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; CHECK: #APP
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; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
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; Now O with -3
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; CHECK: #APP
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; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind
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; Now P with 65535
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; CHECK: #APP
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; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},65535
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; CHECK: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
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; Now R Which takes the address of c
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%c = alloca i32, align 4
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store i32 -4469539, i32* %c, align 4
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%8 = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %c) #1
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; CHECK: #APP
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; CHECK: lwl ${{[0-9]+}}, 1 + 0(${{[0-9]+}})
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; CHECK: lwr ${{[0-9]+}}, 2 + 0(${{[0-9]+}})
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; CHECK: #NO_APP
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ret i32 0
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}
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