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4fc498f43c
These were all using the default 32-bit VALU write class, but the i64/f64 compares are half rate. I'm not sure this is really correct, because they are still using the write to VALU write class, even though they really write to the SALU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248582 91177308-0d34-0410-b5e6-96231b3b80d8
189 lines
5.9 KiB
LLVM
189 lines
5.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; SI-LABEL: @test_if
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; Make sure the i1 values created by the cfg structurizer pass are
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; moved using VALU instructions
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; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
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; SI: v_mov_b32_e32 v{{[0-9]}}, -1
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define void @test_if(i32 %a, i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 {
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entry:
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switch i32 %a, label %default [
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i32 0, label %case0
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i32 1, label %case1
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]
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case0:
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%arrayidx1 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
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store i32 0, i32 addrspace(1)* %arrayidx1, align 4
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br label %end
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case1:
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%arrayidx5 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
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store i32 1, i32 addrspace(1)* %arrayidx5, align 4
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br label %end
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default:
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%cmp8 = icmp eq i32 %a, 2
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%arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
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br i1 %cmp8, label %if, label %else
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if:
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store i32 2, i32 addrspace(1)* %arrayidx10, align 4
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br label %end
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else:
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store i32 3, i32 addrspace(1)* %arrayidx10, align 4
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br label %end
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end:
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ret void
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}
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; SI-LABEL: @simple_test_v_if
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; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
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; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
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; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
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; SI: ; BB#1
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; SI: buffer_store_dword
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; SI: s_endpgm
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; SI: BB1_2:
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; SI: s_or_b64 exec, exec, [[BR_SREG]]
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; SI: s_endpgm
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define void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%is.0 = icmp ne i32 %tid, 0
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br i1 %is.0, label %store, label %exit
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store:
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%gep = getelementptr i32, i32 addrspace(1)* %dst, i32 %tid
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store i32 999, i32 addrspace(1)* %gep
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ret void
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exit:
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ret void
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}
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; SI-LABEL: @simple_test_v_loop
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; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
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; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
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; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
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; SI: s_cbranch_execz BB2_2
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; SI: ; BB#1:
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; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI: BB2_3:
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; SI: buffer_load_dword
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; SI: buffer_store_dword
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; SI: v_cmp_eq_i32_e32 vcc,
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; SI: s_or_b64 [[OR_SREG:s\[[0-9]+:[0-9]+\]]]
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; SI: s_andn2_b64 exec, exec, [[OR_SREG]]
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; SI: s_cbranch_execnz BB2_3
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define void @simple_test_v_loop(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
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entry:
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%is.0 = icmp ne i32 %tid, 0
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%limit = add i32 %tid, 64
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br i1 %is.0, label %loop, label %exit
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loop:
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%i = phi i32 [%tid, %entry], [%i.inc, %loop]
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%gep.src = getelementptr i32, i32 addrspace(1)* %src, i32 %i
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%gep.dst = getelementptr i32, i32 addrspace(1)* %dst, i32 %i
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%load = load i32, i32 addrspace(1)* %src
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store i32 %load, i32 addrspace(1)* %gep.dst
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%i.inc = add nsw i32 %i, 1
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%cmp = icmp eq i32 %limit, %i.inc
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br i1 %cmp, label %exit, label %loop
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exit:
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ret void
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}
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; SI-LABEL: @multi_vcond_loop
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; Load loop limit from buffer
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; Branch to exit if uniformly not taken
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; SI: ; BB#0:
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; SI: buffer_load_dword [[VBOUND:v[0-9]+]]
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; SI: v_cmp_lt_i32_e32 vcc
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; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
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; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]]
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; SI: s_cbranch_execz BB3_2
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; Initialize inner condition to false
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; SI: ; BB#1:
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; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]]
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; Clear exec bits for workitems that load -1s
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; SI: BB3_3:
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; SI: buffer_load_dword [[B:v[0-9]+]]
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; SI: buffer_load_dword [[A:v[0-9]+]]
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; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]]
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; SI-DAG: v_cmp_ne_i32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
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; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
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; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
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; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]]
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; SI: s_cbranch_execz BB3_5
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; SI: BB#4:
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; SI: buffer_store_dword
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; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
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; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
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; SI: BB3_5:
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; SI: s_or_b64 exec, exec, [[ORNEG2]]
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; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
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; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
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; SI: s_cbranch_execnz BB3_3
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; SI: BB#6
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; SI: s_or_b64 exec, exec, [[COND_STATE]]
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; SI: BB3_2:
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; SI-NOT: [[COND_STATE]]
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; SI: s_endpgm
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define void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addrspace(1)* noalias nocapture readonly %arg1, i32 addrspace(1)* noalias nocapture readonly %arg2, i32 addrspace(1)* noalias nocapture readonly %arg3) #1 {
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bb:
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%tmp = tail call i32 @llvm.r600.read.tidig.x() #0
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%tmp4 = sext i32 %tmp to i64
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg3, i64 %tmp4
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%tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
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%tmp7 = icmp sgt i32 %tmp6, 0
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%tmp8 = sext i32 %tmp6 to i64
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br i1 %tmp7, label %bb10, label %bb26
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bb10: ; preds = %bb, %bb20
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%tmp11 = phi i64 [ %tmp23, %bb20 ], [ 0, %bb ]
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%tmp12 = add nsw i64 %tmp11, %tmp4
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%tmp13 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp12
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%tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4
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%tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp12
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%tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
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%tmp17 = icmp ne i32 %tmp14, -1
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%tmp18 = icmp ne i32 %tmp16, -1
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%tmp19 = and i1 %tmp17, %tmp18
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br i1 %tmp19, label %bb20, label %bb26
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bb20: ; preds = %bb10
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%tmp21 = add nsw i32 %tmp16, %tmp14
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%tmp22 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp12
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store i32 %tmp21, i32 addrspace(1)* %tmp22, align 4
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%tmp23 = add nuw nsw i64 %tmp11, 1
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%tmp24 = icmp slt i64 %tmp23, %tmp8
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br i1 %tmp24, label %bb10, label %bb26
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bb26: ; preds = %bb10, %bb20, %bb
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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