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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.8 KiB
C++
63 lines
1.8 KiB
C++
//===-- AMDGPUConvertToISA.cpp - Lower AMDIL to HW ISA --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This pass lowers AMDIL machine instructions to the appropriate
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/// hardware instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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namespace {
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class AMDGPUConvertToISAPass : public MachineFunctionPass {
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private:
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static char ID;
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TargetMachine &TM;
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public:
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AMDGPUConvertToISAPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TM(tm) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {return "AMDGPU Convert to ISA";}
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};
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} // End anonymous namespace
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char AMDGPUConvertToISAPass::ID = 0;
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FunctionPass *llvm::createAMDGPUConvertToISAPass(TargetMachine &tm) {
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return new AMDGPUConvertToISAPass(tm);
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}
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bool AMDGPUConvertToISAPass::runOnMachineFunction(MachineFunction &MF) {
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const AMDGPUInstrInfo * TII =
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static_cast<const AMDGPUInstrInfo*>(TM.getInstrInfo());
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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}
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}
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return false;
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}
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