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c0b9dc5be7
ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
12 KiB
C++
317 lines
12 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using are sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CFG.h"
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#include "Support/DepthFirstIterator.h"
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using namespace llvm;
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static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
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const std::pair<MachineBasicBlock*, unsigned> &
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LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{
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return BBMap.find(MBB->getBasicBlock())->second;
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}
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/// getIndexMachineBasicBlock() - Given a block index, return the
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/// MachineBasicBlock corresponding to it.
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MachineBasicBlock *LiveVariables::getIndexMachineBasicBlock(unsigned Idx) {
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if (BBIdxMap.empty()) {
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BBIdxMap.resize(BBMap.size());
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for (std::map<const BasicBlock*, std::pair<MachineBasicBlock*, unsigned> >
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::iterator I = BBMap.begin(), E = BBMap.end(); I != E; ++I) {
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assert(BBIdxMap.size() > I->second.second &&"Indices are not sequential");
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assert(BBIdxMap[I->second.second] == 0 && "Multiple idx collision!");
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BBIdxMap[I->second.second] = I->second.first;
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}
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}
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assert(Idx < BBIdxMap.size() && "BB Index out of range!");
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return BBIdxMap[Idx];
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}
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
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"getVarInfo: not a virtual register!");
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RegIdx -= MRegisterInfo::FirstVirtualRegister;
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if (RegIdx >= VirtRegInfo.size()) {
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if (RegIdx >= 2*VirtRegInfo.size())
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VirtRegInfo.resize(RegIdx*2);
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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return VirtRegInfo[RegIdx];
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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const BasicBlock *BB) {
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const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
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MachineBasicBlock *MBB = Info.first;
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unsigned BBNum = Info.second;
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it...
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i].first == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == VRInfo.DefBlock) return; // Terminate recursion
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if (VRInfo.AliveBlocks.size() <= BBNum)
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VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
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if (VRInfo.AliveBlocks[BBNum])
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks[BBNum] = true;
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for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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// Check to see if this basic block is already a kill block...
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back().second = MI;
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
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#endif
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assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
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// Add a new kill entry for this basic block.
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VRInfo.Kills.push_back(std::make_pair(MBB, MI));
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// Update all dominating blocks to mark them known live.
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const BasicBlock *BB = MBB->getBasicBlock();
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for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB);
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PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, *PI);
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}
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = true;
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
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if (PhysRegUsed[Reg])
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RegistersKilled.insert(std::make_pair(LastUse, Reg));
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else
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RegistersDead.insert(std::make_pair(LastUse, Reg));
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}
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = false;
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for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
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*AliasSet; ++AliasSet) {
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unsigned Alias = *AliasSet;
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if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
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if (PhysRegUsed[Alias])
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RegistersKilled.insert(std::make_pair(LastUse, Alias));
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else
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RegistersDead.insert(std::make_pair(LastUse, Alias));
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}
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PhysRegInfo[Alias] = MI;
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PhysRegUsed[Alias] = false;
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}
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
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const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
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RegInfo = MF.getTarget().getRegisterInfo();
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assert(RegInfo && "Target doesn't have register information?");
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// First time though, initialize AllocatablePhysicalRegisters for the target
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if (AllocatablePhysicalRegisters.empty()) {
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// Make space, initializing to false...
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AllocatablePhysicalRegisters.resize(RegInfo->getNumRegs());
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// Loop over all of the register classes...
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for (MRegisterInfo::regclass_iterator RCI = RegInfo->regclass_begin(),
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E = RegInfo->regclass_end(); RCI != E; ++RCI)
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// Loop over all of the allocatable registers in the function...
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for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
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E = (*RCI)->allocation_order_end(MF); I != E; ++I)
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AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
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}
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// Build BBMap...
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unsigned BBNum = 0;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++);
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// PhysRegInfo - Keep track of which instruction was the last use of a
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// physical register. This is a purely local property, because all physical
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// register references as presumed dead across basic blocks.
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//
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MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
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bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
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std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
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(MachineInstr*)0);
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PhysRegInfo = PhysRegInfoA;
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PhysRegUsed = PhysRegUsedA;
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/// Get some space for a respectable number of registers...
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VirtRegInfo.resize(64);
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// Calculate live variable information in depth first order on the CFG of the
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// function. This guarantees that we will see the definition of a virtual
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// register before its uses due to dominance properties of SSA (except for PHI
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// nodes, which are treated as a special case).
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//
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const BasicBlock *Entry = MF.getFunction()->begin();
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for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
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DFI != E; ++DFI) {
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const BasicBlock *BB = *DFI;
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std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second;
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MachineBasicBlock *MBB = BBRec.first;
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unsigned BBNum = BBRec.second;
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// Loop over all of the instructions, processing them.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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MachineInstr *MI = I;
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const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
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// Process all of the operands of the instruction...
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unsigned NumOperandsToProcess = MI->getNumOperands();
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// Unless it is a PHI node. In this case, ONLY process the DEF, not any
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// of the uses. They will be handled in other basic blocks.
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if (MI->getOpcode() == TargetInstrInfo::PHI)
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NumOperandsToProcess = 1;
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// Loop over implicit uses, using them.
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for (const unsigned *ImplicitUses = MID.ImplicitUses;
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*ImplicitUses; ++ImplicitUses)
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HandlePhysRegUse(*ImplicitUses, MI);
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// Process all explicit uses...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isUse() && MO.isRegister()) {
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if (MRegisterInfo::isVirtualRegister(MO.getReg())){
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HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
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} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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AllocatablePhysicalRegisters[MO.getReg()]) {
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HandlePhysRegUse(MO.getReg(), MI);
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}
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}
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}
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// Loop over implicit defs, defining them.
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for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
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*ImplicitDefs; ++ImplicitDefs)
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HandlePhysRegDef(*ImplicitDefs, MI);
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// Process all explicit defs...
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for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isDef() && MO.isRegister()) {
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if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
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VarInfo &VRInfo = getVarInfo(MO.getReg());
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assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
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VRInfo.DefBlock = MBB; // Created here...
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VRInfo.DefInst = MI;
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VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
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} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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AllocatablePhysicalRegisters[MO.getReg()]) {
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HandlePhysRegDef(MO.getReg(), MI);
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}
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}
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}
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}
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// Handle any virtual assignments from PHI nodes which might be at the
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// bottom of this basic block. We check all of our successor blocks to see
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// if they have PHI nodes, and if so, we simulate an assignment at the end
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// of the current block.
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for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB);
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SI != E; ++SI) {
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MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
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// PHI nodes are guaranteed to be at the top of the block...
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for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
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MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
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for (unsigned i = 1; ; i += 2)
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if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.getVRegValueOrNull()) {
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VarInfo &VRInfo = getVarInfo(MO.getReg());
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// Only mark it alive only in the block we are representing...
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MarkVirtRegAliveInBlock(VRInfo, BB);
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break; // Found the PHI entry for this block...
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}
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}
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}
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}
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// Loop over PhysRegInfo, killing any registers that are available at the
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// end of the basic block. This also resets the PhysRegInfo map.
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for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
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if (PhysRegInfo[i])
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HandlePhysRegDef(i, 0);
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}
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// Convert the information we have gathered into VirtRegInfo and transform it
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// into a form usable by RegistersKilled.
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//
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for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
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for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
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if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
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RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
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i + MRegisterInfo::FirstVirtualRegister));
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else
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RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
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i + MRegisterInfo::FirstVirtualRegister));
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}
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return false;
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}
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