Chris Dewhurst 9343ace500 This change adds co-processor condition branching and conditional traps to the Sparc back-end. ... This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263044 91177308-0d34-0410-b5e6-96231b3b80d8		2016-03-09 18:20:21 +00:00
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AArch64	[AArch64] Add ARMv8.2-A FP16 vector instructions	2015-12-08 12:16:10 +00:00
AMDGPU	[AMDGPU] Disassembler: Support for all VOP1 instructions.	2016-02-25 16:09:14 +00:00
ARM	[ARM] Add new system registers to ARMv8-M Baseline/Mainline	2016-01-25 11:25:36 +00:00
Hexagon	[Hexagon] Fixing store instructions and reenabling a few more tests.	2015-11-10 00:22:00 +00:00
Mips	[mips] Range check uimm20 and fixed a bug this revealed.	2016-02-29 16:06:38 +00:00
PowerPC	[Power9] Implement new vsx instructions: load, store instructions for vector and scalar	2016-03-08 03:49:13 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features	2015-10-01 14:43:48 +00:00
X86	AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.	2016-02-25 13:30:17 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00