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6b1d32c6d7
This fixes 17 of the 41 -verify-machineinstrs test failures identified in PR33045 Differential Revision: https://reviews.llvm.org/D33451 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303691 91177308-0d34-0410-b5e6-96231b3b80d8
404 lines
12 KiB
LLVM
404 lines
12 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}store_i1:
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; EG: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT MSKOR
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; GCN: buffer_store_byte
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define amdgpu_kernel void @store_i1(i1 addrspace(1)* %out) {
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entry:
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store i1 true, i1 addrspace(1)* %out
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ret void
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}
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; i8 store
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; FUNC-LABEL: {{^}}store_i8:
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; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
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; EG-NOT: MEM_RAT MSKOR
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; IG 0: Get the byte index and truncate the value
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; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
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; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
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; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
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; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
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; IG 1: Truncate the calculated the shift amount for the mask
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; IG 2: Shift the value and the mask
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; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
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; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
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; EG-NEXT: 255
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; IG 3: Initialize the Y and Z channels to zero
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; XXX: An optimal scheduler should merge this into one of the prevous IGs.
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; EG: MOV T[[RW_GPR]].Y, 0.0
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; EG: MOV * T[[RW_GPR]].Z, 0.0
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; GCN: buffer_store_byte
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define amdgpu_kernel void @store_i8(i8 addrspace(1)* %out, i8 %in) {
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entry:
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store i8 %in, i8 addrspace(1)* %out
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ret void
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}
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; i16 store
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; FUNC-LABEL: {{^}}store_i16:
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; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
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; EG-NOT: MEM_RAT MSKOR
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; IG 0: Get the byte index and truncate the value
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; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
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; EG-NEXT: 3(4.203895e-45),
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; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
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; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
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; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
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; IG 1: Truncate the calculated the shift amount for the mask
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; IG 2: Shift the value and the mask
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; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
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; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
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; EG-NEXT: 65535
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; IG 3: Initialize the Y and Z channels to zero
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; XXX: An optimal scheduler should merge this into one of the prevous IGs.
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; EG: MOV T[[RW_GPR]].Y, 0.0
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; EG: MOV * T[[RW_GPR]].Z, 0.0
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; GCN: buffer_store_short
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define amdgpu_kernel void @store_i16(i16 addrspace(1)* %out, i16 %in) {
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entry:
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store i16 %in, i16 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_i24:
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; GCN: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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; GCN-DAG: buffer_store_byte
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; GCN-DAG: buffer_store_short
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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define amdgpu_kernel void @store_i24(i24 addrspace(1)* %out, i24 %in) {
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entry:
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store i24 %in, i24 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_i25:
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; GCN: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}}
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; GCN: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]
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; GCN: buffer_store_dword [[VAND]]
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; EG-NOT: MEM_RAT
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; CM-NOT: MEM_RAT
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define amdgpu_kernel void @store_i25(i25 addrspace(1)* %out, i25 %in) {
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entry:
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store i25 %in, i25 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v2i8:
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; v2i8 is naturally 2B aligned
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; EG: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT MSKOR
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; GCN: buffer_store_short
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define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
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entry:
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%0 = trunc <2 x i32> %in to <2 x i8>
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store <2 x i8> %0, <2 x i8> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v2i8_unaligned:
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT MSKOR
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; SI: buffer_store_byte
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define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
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entry:
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%0 = trunc <2 x i32> %in to <2 x i8>
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store <2 x i8> %0, <2 x i8> addrspace(1)* %out, align 1
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ret void
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}
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; FUNC-LABEL: {{^}}store_v2i16:
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; GCN: buffer_store_dword
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define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
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entry:
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%0 = trunc <2 x i32> %in to <2 x i16>
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store <2 x i16> %0, <2 x i16> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v2i16_unaligned:
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; SI: buffer_store_short
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; SI: buffer_store_short
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define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
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entry:
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%0 = trunc <2 x i32> %in to <2 x i16>
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store <2 x i16> %0, <2 x i16> addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: {{^}}store_v4i8:
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; GCN: buffer_store_dword
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define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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%0 = trunc <4 x i32> %in to <4 x i8>
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store <4 x i8> %0, <4 x i8> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v4i8_unaligned:
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI-NOT: buffer_store_dword
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define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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%0 = trunc <4 x i32> %in to <4 x i8>
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store <4 x i8> %0, <4 x i8> addrspace(1)* %out, align 1
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ret void
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}
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; FUNC-LABEL: {{^}}store_v4i8_halfaligned:
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; EG: MEM_RAT MSKOR
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; EG: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT MSKOR
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT MSKOR
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; SI: buffer_store_short
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; SI: buffer_store_short
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; SI-NOT: buffer_store_dword
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define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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%0 = trunc <4 x i32> %in to <4 x i8>
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store <4 x i8> %0, <4 x i8> addrspace(1)* %out, align 2
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ret void
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}
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; floating-point store
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; FUNC-LABEL: {{^}}store_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
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; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
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; GCN: buffer_store_dword
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define amdgpu_kernel void @store_f32(float addrspace(1)* %out, float %in) {
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store float %in, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v4i16:
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; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
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; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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%0 = trunc <4 x i32> %in to <4 x i16>
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store <4 x i16> %0, <4 x i16> addrspace(1)* %out
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ret void
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}
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; vec2 floating-point stores
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; FUNC-LABEL: {{^}}store_v2f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
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%1 = insertelement <2 x float> %0, float %b, i32 1
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store <2 x float> %1, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v3i32:
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; GCN-DAG: buffer_store_dwordx2
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; GCN-DAG: buffer_store_dword v
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; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}},
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; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XY}}, {{T[0-9]+\.[XYZW]}},
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define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {
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store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}store_v4i32:
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; EG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XYZW}}
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_v4i32_unaligned:
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; EG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XYZW}}
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; SI: buffer_store_dwordx4
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define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
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entry:
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store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; v4f32 store
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; FUNC-LABEL: {{^}}store_v4f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%1 = load <4 x float>, <4 x float> addrspace(1) * %in
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store <4 x float> %1, <4 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_i64_i8:
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; EG: MEM_RAT MSKOR
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; CM: MEM_RAT MSKOR
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; GCN: buffer_store_byte
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define amdgpu_kernel void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) {
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entry:
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%0 = trunc i64 %in to i8
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store i8 %0, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}store_i64_i16:
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; EG: MEM_RAT MSKOR
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; GCN: buffer_store_short
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define amdgpu_kernel void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) {
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entry:
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%0 = trunc i64 %in to i16
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store i16 %0, i16 addrspace(1)* %out
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ret void
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}
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; The stores in this function are combined by the optimizer to create a
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; 64-bit store with 32-bit alignment. This is legal and the legalizer
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; should not try to split the 64-bit store back into 2 32-bit stores.
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; FUNC-LABEL: {{^}}vecload2:
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; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XY, T[0-9]+\.X}}, 1
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; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
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; CM: MEM_RAT_CACHELESS STORE_DWORD
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; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
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entry:
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%0 = load i32, i32 addrspace(2)* %mem, align 4
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%arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
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%1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
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store i32 %0, i32 addrspace(1)* %out, align 4
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%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
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store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
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ret void
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}
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; When i128 was a legal type this program generated cannot select errors:
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; FUNC-LABEL: {{^}}"i128-const-store":
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; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 1
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; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}, T{{[0-9]+}}.X
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @i128-const-store(i32 addrspace(1)* %out) {
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entry:
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store i32 1, i32 addrspace(1)* %out, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
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store i32 1, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx4 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2
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store i32 2, i32 addrspace(1)* %arrayidx4, align 4
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%arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 3
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store i32 2, i32 addrspace(1)* %arrayidx6, align 4
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ret void
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}
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attributes #0 = { nounwind }
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