Bob Wilson 46455096be Remove DAG combiner patch to fold vector splats. Instcombiner does it now. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117720 91177308-0d34-0410-b5e6-96231b3b80d8

2010-10-29 22:03:02 +00:00

..

CMakeLists.txt

Removed a bunch of unnecessary target_link_libraries.

2010-09-28 22:39:14 +00:00

DAGCombiner.cpp

Remove DAG combiner patch to fold vector splats. Instcombiner does it now.

2010-10-29 22:03:02 +00:00

FastISel.cpp

Use frame index, if available for byval argument while lowering dbg_declare. Otherwise let getRegForValue() find register for this argument.

2010-09-14 20:29:31 +00:00

FunctionLoweringInfo.cpp

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InstrEmitter.cpp

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InstrEmitter.h

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LegalizeDAG.cpp

Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any

2010-10-19 23:27:08 +00:00

LegalizeFloatTypes.cpp

update a bunch of code to use the MachinePointerInfo version of getStore.

2010-09-21 18:41:36 +00:00

LegalizeIntegerTypes.cpp

propagate MachinePointerInfo through various uses of the old

2010-09-21 17:04:51 +00:00

LegalizeTypes.cpp

continue MachinePointerInfo'izing, eliminating use of one of the old

2010-09-21 16:36:31 +00:00

LegalizeTypes.h

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LegalizeTypesGeneric.cpp

update a bunch of code to use the MachinePointerInfo version of getStore.

2010-09-21 18:41:36 +00:00

LegalizeVectorOps.cpp

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LegalizeVectorTypes.cpp

Remove Synthesizable from the Type system; as MMX vector

2010-10-20 21:32:10 +00:00

Makefile

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ScheduleDAGFast.cpp

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ScheduleDAGList.cpp

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ScheduleDAGRRList.cpp

Avoiding overly aggressive latency scheduling. If the two nodes share an

2010-10-29 18:09:28 +00:00

ScheduleDAGSDNodes.cpp

Avoiding overly aggressive latency scheduling. If the two nodes share an

2010-10-29 18:09:28 +00:00

ScheduleDAGSDNodes.h

Teach if-converter to be more careful with predicating instructions that would

2010-09-10 01:29:16 +00:00

SDNodeDbgValue.h

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SDNodeOrdering.h

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SelectionDAG.cpp

Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches

2010-10-26 23:11:10 +00:00

SelectionDAGBuilder.cpp

Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.

2010-10-29 17:29:13 +00:00

SelectionDAGBuilder.h

When isel is emitting instructions for an x86 target without CMOV, the CFG is

2010-09-30 19:44:31 +00:00

SelectionDAGISel.cpp

For statistics that are only used in functions declared in !NDEBUG, wrap the

2010-10-26 00:51:57 +00:00

SelectionDAGPrinter.cpp

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TargetLowering.cpp

Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.

2010-10-29 17:29:13 +00:00

TargetSelectionDAGInfo.cpp

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