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ea7a0c0467
This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265589 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}main:
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; GCN: v_cvt_pkrtz_f16_f32
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; GCN: v_cvt_pkrtz_f16_f32
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; GCN-NOT: v_cvt_pkrtz_f16_f32
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define amdgpu_ps void @main(float %src) {
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main_body:
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%p1 = call i32 @llvm.SI.packf16(float undef, float %src)
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%p2 = call i32 @llvm.SI.packf16(float %src, float undef)
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%p3 = call i32 @llvm.SI.packf16(float undef, float undef)
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%f1 = bitcast i32 %p1 to float
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%f2 = bitcast i32 %p2 to float
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%f3 = bitcast i32 %p3 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 0, i32 0, i32 1, float undef, float %f1, float undef, float %f1)
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call void @llvm.SI.export(i32 15, i32 1, i32 0, i32 0, i32 1, float undef, float %f2, float undef, float %f2)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %f3, float undef, float %f2)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #0
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { nounwind readnone }
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