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16cba6923a
When FastISel fails to translate an instruction it hands off code generation to SelectionDAG. Before it does so, it may have generated local value instructions to feed phi nodes in successor blocks. These instructions will then be generated again by SelectionDAG, causing duplication and less efficient code, including extra spill instructions. Patch by Wolfgang Pieb! Differential Revision: http://reviews.llvm.org/D11768 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255520 91177308-0d34-0410-b5e6-96231b3b80d8
148 lines
5.6 KiB
LLVM
148 lines
5.6 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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;
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; Generated with clang -O2 -S -emit-llvm
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;
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; /* Test 1 */
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; extern "C" bool bar (long double);
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; __attribute__((optnone))
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; extern "C" bool foo(long double x, long double y)
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; {
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; return (x == y) || (bar(x));
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; }
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;
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; /* Test 2 */
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; struct FVector {
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; float x, y, z;
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; inline __attribute__((always_inline)) FVector(float f): x(f), y(f), z(f) {}
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; inline __attribute__((always_inline)) FVector func(float p) const
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; {
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; if( x == 1.f ) {
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; return *this;
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; } else if( x < p ) {
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; return FVector(0.f);
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; }
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; return FVector(x);
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; }
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; };
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;
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; __attribute__((optnone))
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; int main()
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; {
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; FVector v(1.0);
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; v = v.func(1.e-8);
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; return 0;
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; }
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;
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; ModuleID = 'test.cpp'
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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%struct.FVector = type { float, float, float }
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define zeroext i1 @foo(x86_fp80 %x, x86_fp80 %y) noinline optnone {
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entry:
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%x.addr = alloca x86_fp80, align 16
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%y.addr = alloca x86_fp80, align 16
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store x86_fp80 %x, x86_fp80* %x.addr, align 16
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store x86_fp80 %y, x86_fp80* %y.addr, align 16
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%0 = load x86_fp80, x86_fp80* %x.addr, align 16
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%1 = load x86_fp80, x86_fp80* %y.addr, align 16
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%cmp = fcmp oeq x86_fp80 %0, %1
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; Test 1
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; Make sure that there is no dead code generated
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; from Fast-ISel Phi-node handling. We should only
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; see one movb of the constant 1, feeding the PHI
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; node in lor.end. This covers the code path with
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; handlePHINodesInSuccessorBlocks() returning true.
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;
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; CHECK-LABEL: foo:
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; CHECK: movb $1,
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; CHECK-NOT: movb $1,
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; CHECK-LABEL: .LBB0_1:
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br i1 %cmp, label %lor.end, label %lor.rhs
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lor.rhs: ; preds = %entry
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%2 = load x86_fp80, x86_fp80* %x.addr, align 16
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%call = call zeroext i1 @bar(x86_fp80 %2)
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %entry
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%3 = phi i1 [ true, %entry ], [ %call, %lor.rhs ]
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ret i1 %3
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}
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declare zeroext i1 @bar(x86_fp80)
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define i32 @main() noinline optnone {
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entry:
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%retval = alloca i32, align 4
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%v = alloca %struct.FVector, align 4
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%ref.tmp = alloca %struct.FVector, align 4
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%tmp = alloca { <2 x float>, float }, align 8
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store i32 0, i32* %retval, align 4
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%0 = bitcast %struct.FVector* %v to i8*
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call void @llvm.lifetime.start(i64 12, i8* %0) nounwind
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%x.i = getelementptr inbounds %struct.FVector, %struct.FVector* %v, i64 0, i32 0
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store float 1.000000e+00, float* %x.i, align 4
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%y.i = getelementptr inbounds %struct.FVector, %struct.FVector* %v, i64 0, i32 1
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store float 1.000000e+00, float* %y.i, align 4
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%z.i = getelementptr inbounds %struct.FVector, %struct.FVector* %v, i64 0, i32 2
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store float 1.000000e+00, float* %z.i, align 4
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%x.i.1 = getelementptr inbounds %struct.FVector, %struct.FVector* %v, i64 0, i32 0
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%1 = load float, float* %x.i.1, align 4
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%cmp.i = fcmp oeq float %1, 1.000000e+00
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br i1 %cmp.i, label %if.then.i, label %if.else.i
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if.then.i: ; preds = %entry
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%retval.sroa.0.0..sroa_cast.i = bitcast %struct.FVector* %v to <2 x float>*
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%retval.sroa.0.0.copyload.i = load <2 x float>, <2 x float>* %retval.sroa.0.0..sroa_cast.i, align 4
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%retval.sroa.6.0..sroa_idx16.i = getelementptr inbounds %struct.FVector, %struct.FVector* %v, i64 0, i32 2
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%retval.sroa.6.0.copyload.i = load float, float* %retval.sroa.6.0..sroa_idx16.i, align 4
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br label %func.exit
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if.else.i: ; preds = %entry
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; Test 2
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; In order to feed the first PHI node in func.exit handlePHINodesInSuccessorBlocks()
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; generates a local value instruction, but it cannot handle the second PHI node and
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; returns false to let SelectionDAGISel handle both cases. Make sure the generated
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; local value instruction is removed.
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; CHECK-LABEL: main:
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; CHECK-LABEL: .LBB1_2:
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; CHECK: xorps [[REG:%xmm[0-7]]], [[REG]]
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; CHECK-NOT: xorps [[REG]], [[REG]]
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; CHECK-LABEL: .LBB1_3:
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%cmp3.i = fcmp olt float %1, 0x3E45798EE0000000
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br i1 %cmp3.i, label %func.exit, label %if.end.5.i
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if.end.5.i: ; preds = %if.else.i
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%retval.sroa.0.0.vec.insert13.i = insertelement <2 x float> undef, float %1, i32 0
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%retval.sroa.0.4.vec.insert15.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert13.i, float %1, i32 1
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br label %func.exit
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func.exit: ; preds = %if.then.i, %if.else.i, %if.end.5.i
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%retval.sroa.6.0.i = phi float [ %retval.sroa.6.0.copyload.i, %if.then.i ], [ %1, %if.end.5.i ], [ 0.000000e+00, %if.else.i ]
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%retval.sroa.0.0.i = phi <2 x float> [ %retval.sroa.0.0.copyload.i, %if.then.i ], [ %retval.sroa.0.4.vec.insert15.i, %if.end.5.i ], [ zeroinitializer, %if.else.i ]
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%.fca.0.insert.i = insertvalue { <2 x float>, float } undef, <2 x float> %retval.sroa.0.0.i, 0
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%.fca.1.insert.i = insertvalue { <2 x float>, float } %.fca.0.insert.i, float %retval.sroa.6.0.i, 1
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store { <2 x float>, float } %.fca.1.insert.i, { <2 x float>, float }* %tmp, align 8
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%2 = bitcast { <2 x float>, float }* %tmp to i8*
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%3 = bitcast %struct.FVector* %ref.tmp to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %3, i8* %2, i64 12, i32 4, i1 false)
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%4 = bitcast %struct.FVector* %v to i8*
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%5 = bitcast %struct.FVector* %ref.tmp to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %4, i8* %5, i64 12, i32 4, i1 false)
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%6 = bitcast %struct.FVector* %v to i8*
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call void @llvm.lifetime.end(i64 12, i8* %6) nounwind
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ret i32 0
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}
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declare void @llvm.lifetime.start(i64, i8* nocapture) argmemonly nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) argmemonly nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture) argmemonly nounwind
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