Chris Dewhurst 97e51dbbfc The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. ... These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262133 91177308-0d34-0410-b5e6-96231b3b80d8		2016-02-27 12:49:59 +00:00
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CMakeLists.txt
LLVMBuild.txt	LLVMBuild.txt: Reformat.	2014-04-10 11:16:17 +00:00
SparcAsmParser.cpp	The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.	2016-02-27 12:49:59 +00:00