James Y Knight 8d30502e60 Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass. ...

Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1
or 2-byte. For those, you need to mask and shift the 1 or 2 byte values
appropriately to use the 4-byte instruction.

This change adds support for cmpxchg-based instruction sets (only SPARC,
in LLVM). The support can be extended for LL/SC-based PPC and MIPS in
the future, supplanting the ISel expansions those architectures
currently use.

Tests added for the IR transform and SPARCv9.

Differential Revision: http://reviews.llvm.org/D21029

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273025 91177308-0d34-0410-b5e6-96231b3b80d8

2016-06-17 18:11:48 +00:00

..

ARM

ARM: use a pseudo-instruction for cmpxchg at -O0.

2016-04-18 21:48:55 +00:00

SPARC

Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass.

2016-06-17 18:11:48 +00:00

X86

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