Rafael Espindola 9c3d5a70f4 Now that RegistersDefinedFromSameValue handles one instruction being an ... implicit_def, the other instruction can be anything, including instructions that define multiple values. Be careful about that and don't assume what operand 0 is. Fixes pr13249. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159509 91177308-0d34-0410-b5e6-96231b3b80d8		2012-07-01 17:08:01 +00:00
..
ARM	Now that RegistersDefinedFromSameValue handles one instruction being an	2012-07-01 17:08:01 +00:00
CellSPU
CPP
Generic	add a new @llvm.donothing intrinsic that, well, does nothing, and teach CodeGen to ignore calls to it	2012-06-28 22:30:12 +00:00
Hexagon
MBlaze
Mips	The Mips specific inline asm operand modifier 'z' has the	2012-06-28 01:33:40 +00:00
MSP430
NVPTX
PowerPC
SPARC
Thumb
Thumb2
X86	Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2.	2012-07-01 06:12:26 +00:00
XCore