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9e3e730417
r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182960 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
939 B
LLVM
51 lines
939 B
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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define i32 @shl() nounwind ssp {
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entry:
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; ARM: shl
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; ARM: lsl r0, r0, #2
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%shl = shl i32 -1, 2
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ret i32 %shl
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}
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define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: shl_reg
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; ARM: lsl r0, r0, r1
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%shl = shl i32 %src1, %src2
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ret i32 %shl
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}
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define i32 @lshr() nounwind ssp {
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entry:
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; ARM: lshr
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; ARM: lsr r0, r0, #2
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%lshr = lshr i32 -1, 2
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ret i32 %lshr
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}
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define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: lshr_reg
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; ARM: lsr r0, r0, r1
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%lshr = lshr i32 %src1, %src2
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ret i32 %lshr
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}
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define i32 @ashr() nounwind ssp {
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entry:
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; ARM: ashr
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; ARM: asr r0, r0, #2
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%ashr = ashr i32 -1, 2
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ret i32 %ashr
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}
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define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ARM: ashr_reg
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; ARM: asr r0, r0, r1
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%ashr = ashr i32 %src1, %src2
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ret i32 %ashr
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}
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