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a0f5bf306c
This is the first incremental patch to implement this feature. It adds no functionality to LLVM but setup up the information needed from targets in order to implement the optimization correctly. Each target needs to specify the maximum number of store operations for conversion of the llvm.memset, llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations. The limit needs to be chosen at the threshold of performance for such an optimization (generally smallish). The target also needs to specify whether the target can support unaligned stores for multi-byte store operations. This helps ensure the optimization doesn't generate code that will trap on an alignment errors. More patches to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22468 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| Alpha | ||
| CBackend | ||
| IA64 | ||
| PowerPC | ||
| Skeleton | ||
| Sparc | ||
| SparcV8 | ||
| SparcV9 | ||
| X86 | ||
| Makefile | ||
| MRegisterInfo.cpp | ||
| Target.td | ||
| TargetData.cpp | ||
| TargetFrameInfo.cpp | ||
| TargetInstrInfo.cpp | ||
| TargetMachine.cpp | ||
| TargetMachineRegistry.cpp | ||
| TargetSchedInfo.cpp | ||
| TargetSubtarget.cpp | ||