Petar Jovanovic 2d829cd8cb Revert r306095: [mips] Fix reg positions in the aui/daui instructions ...

ELF/mips-plt-r6.s in lld-test is failing. Reverting the change.

Original commit message:

  [mips] Fix register positions in the aui/daui instructions

  Swapped the position of the rt and rs register in the aut/daui
  instructions for mips32r6 and mips64r6. With this change, the format of
  the generated instructions complies with specifications and GCC.
  Patch by Milos Stojanovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306099 91177308-0d34-0410-b5e6-96231b3b80d8

2017-06-23 13:33:46 +00:00

..

AArch64

[AArch64] armv8-A doesn't have CRC.

2017-05-03 20:33:52 +00:00

AMDGPU

[AMDGPU] Add intrinsics for tbuffer load and store

2017-06-22 16:29:22 +00:00

ARM

[ARM] Saturation instructions are DSP-only

2016-07-25 22:25:25 +00:00

Hexagon

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

Lanai

[lanai] Add Lanai backend.

2016-03-28 13:09:54 +00:00

Mips

Revert r306095: [mips] Fix reg positions in the aui/daui instructions

2017-06-23 13:33:46 +00:00

PowerPC

[Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.

2017-06-12 17:58:42 +00:00

Sparc

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

2016-03-09 18:20:21 +00:00

SystemZ

[SystemZ] Add decimal floating-point instructions

2017-05-30 10:15:16 +00:00

X86

[X86] Adding vpopcntd and vpopcntq instructions

2017-05-25 13:45:23 +00:00

XCore

…