Tim Northover 5af1d0751a GlobalISel: add some more sanity-checking to MachineInstrBuilder. NFC. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306481 91177308-0d34-0410-b5e6-96231b3b80d8

2017-06-27 22:45:35 +00:00

..

CallLowering.cpp

[IR] Abstract away ArgNo+1 attribute indexing as much as possible

2017-05-03 18:17:31 +00:00

CMakeLists.txt

Prune trailing whitespace. (To regenerate makefiles)

2017-05-28 22:54:25 +00:00

GlobalISel.cpp

[GlobalISel] Add a localizer pass for target to use

2017-05-27 01:34:00 +00:00

InstructionSelect.cpp

ARM: Compute MaxCallFrame size early

2017-05-05 22:04:05 +00:00

InstructionSelector.cpp

[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-06-26 22:44:03 +00:00

IRTranslator.cpp

[GISel]: Add G_FEXP, G_FEXP2 opcodes

2017-06-27 22:19:32 +00:00

Legalizer.cpp

GlobalISel: remove G_SEQUENCE instruction.

2017-06-23 16:15:55 +00:00

LegalizerHelper.cpp

AArch64: legalize G_EXTRACT operations.

2017-06-26 20:34:13 +00:00

LegalizerInfo.cpp

[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

2017-06-26 22:44:03 +00:00

LLVMBuild.txt

…

Localizer.cpp

[Localizer] Don't trick to be smart for the insertion point

2017-05-30 20:53:06 +00:00

MachineIRBuilder.cpp

GlobalISel: add some more sanity-checking to MachineInstrBuilder. NFC.

2017-06-27 22:45:35 +00:00

RegBankSelect.cpp

GlobalISel: verify that a COPY is trivial when created.

2017-06-27 21:41:40 +00:00

RegisterBank.cpp

Move size and alignment information of regclass to TargetRegisterInfo

2017-04-24 18:55:33 +00:00

RegisterBankInfo.cpp

[RegisterBankInfo] Uniquely allocate instruction mapping.

2017-05-05 22:48:22 +00:00

Utils.cpp

[globalisel][tablegen] Add support for COPY_TO_REGCLASS.

2017-06-20 12:36:34 +00:00