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664a3a9314
xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274802 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
2.0 KiB
LLVM
81 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; rdar://7329206
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; Use sbb x, x to materialize carry bit in a GPR. The value is either
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; all 1's or all 0's.
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define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: xorl %eax, %eax
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; CHECK: seta %al
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; CHECK: shll $5, %eax
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%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.1.0
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}
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define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: sbbl %eax, %eax
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; CHECK: andl $32, %eax
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%0 = icmp ult i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.0.0
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}
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define i64 @t3(i64 %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: sbbq %rax, %rax
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; CHECK: andl $64, %eax
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%0 = icmp ult i64 %x, 18 ; <i1> [#uses=1]
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%iftmp.2.0 = select i1 %0, i64 64, i64 0 ; <i64> [#uses=1]
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ret i64 %iftmp.2.0
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}
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@v4 = common global i32 0, align 4
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define i32 @t4(i32 %a) {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: movq _v4@GOTPCREL(%rip), %rax
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; CHECK: cmpl $1, (%rax)
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; CHECK: sbbl %eax, %eax
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; CHECK: andl $32768, %eax
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; CHECK: leal 65536(%rax,%rax), %eax
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%0 = load i32, i32* @v4, align 4
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%not.tobool = icmp eq i32 %0, 0
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%conv.i = sext i1 %not.tobool to i16
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%call.lobit = lshr i16 %conv.i, 15
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%add.i.1 = add nuw nsw i16 %call.lobit, 1
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%conv4.2 = zext i16 %add.i.1 to i32
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%add = shl nuw nsw i32 %conv4.2, 16
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ret i32 %add
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}
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define i8 @t5(i32 %a) #0 {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: testl %edi, %edi
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; CHECK: setns %al
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%.lobit = lshr i32 %a, 31
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%trunc = trunc i32 %.lobit to i8
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%.not = xor i8 %trunc, 1
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ret i8 %.not
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}
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define zeroext i1 @t6(i32 %a) #0 {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: testl %edi, %edi
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; CHECK: setns %al
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%.lobit = lshr i32 %a, 31
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%trunc = trunc i32 %.lobit to i1
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%.not = xor i1 %trunc, 1
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ret i1 %.not
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}
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attributes #0 = { "target-cpu"="skylake-avx512" }
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