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c1359c9fbb
Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277169 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
933 B
LLVM
30 lines
933 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
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; Simple vector total.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: add([[REG:r([0-9]+)]], r{{[0-9]+}})
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; CHECK-NEXT: add(r{{[0-9]+}}, #4)
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; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0)
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; CHECK-NEXT: endloop0
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define i32 @foo(i32* %a, i32 %n) {
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entry:
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br label %for.body
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for.body:
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%sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
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%i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%0 = load i32, i32* %arrayidx.phi, align 4
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%add = add nsw i32 %0, %sum.02
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%inc = add nsw i32 %i.01, 1
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%exitcond = icmp eq i32 %inc, 10000
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%arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret i32 %add
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}
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