Wesley Peck a70f28ce7d Adding the MicroBlaze backend. ... The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8		2010-02-23 19:15:24 +00:00
..
Alpha	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
ARM	Use NEON vmin/vmax instructions for floating-point selects.	2010-02-18 06:05:53 +00:00
Blackfin	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
CBackend	Eliminate more uses of llvm-as and llvm-dis.	2009-09-09 00:09:15 +00:00
CellSPU	don't let asm-verbose break the check-next lines in these tests.	2010-01-19 06:39:54 +00:00
CPP	fix PR5295 where the .ll parser didn't reject a function after a global	2009-10-25 23:22:50 +00:00
Generic	Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there	2010-02-15 22:35:59 +00:00
MBlaze	Adding the MicroBlaze backend.	2010-02-23 19:15:24 +00:00
Mips	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
MSP430	no need to run llvm-as here.	2010-02-22 23:34:12 +00:00
PIC16	emit integer and fp zeros as (e.g.) .byte 0 instead of .space 1,	2010-01-20 07:19:19 +00:00
PowerPC	When emitting an instruction which depends on both a post-incremented	2010-02-22 03:59:54 +00:00
SPARC	add support for the sparcv9-*-* target triple to turn on	2010-02-04 06:34:01 +00:00
SystemZ	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
Thumb	Run the pre-register allocation tail duplication pass by default. Remove	2010-01-16 00:29:50 +00:00
Thumb2	Last week we were generating code with duplicate induction variables in this	2010-02-15 21:56:40 +00:00
X86	These should not have been committed.	2010-02-22 23:37:48 +00:00
XCore	Lower BR_JT on the XCore to a jump into a series of jump instructions.	2010-02-23 13:25:07 +00:00