Sanjay Patel 7b05e5c94e [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433) ...

This should fix:
https://llvm.org/bugs/show_bug.cgi?id=30433

There are a couple of open questions about the codegen:
1. Should we let scalar ops be scalars and avoid vector constant loads/splats?
2. Should we have a pass to combine constants such as the inverted pair that we have here?

Differential Revision: https://reviews.llvm.org/D25165
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283119 91177308-0d34-0410-b5e6-96231b3b80d8

2016-10-03 16:38:27 +00:00

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AArch64

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AMDGPU

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ARM

[TTI] The cost model should not assume vector casts get completely scalarized

2016-07-06 17:30:56 +00:00

PowerPC

[TTI] The cost model should not assume vector casts get completely scalarized

2016-07-06 17:30:56 +00:00

X86

[x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433)

2016-10-03 16:38:27 +00:00

no_info.ll

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