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9343ace500
This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263044 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
5.3 KiB
C++
168 lines
5.3 KiB
C++
//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// Sparc back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_SPARC_H
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#define LLVM_LIB_TARGET_SPARC_SPARC_H
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#include "MCTargetDesc/SparcMCTargetDesc.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class SparcTargetMachine;
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class formatted_raw_ostream;
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class AsmPrinter;
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class MCInst;
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class MachineInstr;
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FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
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FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
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void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI,
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AsmPrinter &AP);
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} // end namespace llvm;
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namespace llvm {
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// Enums corresponding to Sparc condition codes, both icc's and fcc's. These
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// values must be kept in sync with the ones in the .td file.
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namespace SPCC {
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enum CondCodes {
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ICC_A = 8 , // Always
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ICC_N = 0 , // Never
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ICC_NE = 9 , // Not Equal
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ICC_E = 1 , // Equal
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ICC_G = 10 , // Greater
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ICC_LE = 2 , // Less or Equal
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ICC_GE = 11 , // Greater or Equal
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ICC_L = 3 , // Less
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ICC_GU = 12 , // Greater Unsigned
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ICC_LEU = 4 , // Less or Equal Unsigned
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ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned
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ICC_CS = 5 , // Carry Set/Less Unsigned
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ICC_POS = 14 , // Positive
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ICC_NEG = 6 , // Negative
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ICC_VC = 15 , // Overflow Clear
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ICC_VS = 7 , // Overflow Set
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FCC_A = 8+16, // Always
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FCC_N = 0+16, // Never
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FCC_U = 7+16, // Unordered
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FCC_G = 6+16, // Greater
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FCC_UG = 5+16, // Unordered or Greater
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FCC_L = 4+16, // Less
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FCC_UL = 3+16, // Unordered or Less
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FCC_LG = 2+16, // Less or Greater
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FCC_NE = 1+16, // Not Equal
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FCC_E = 9+16, // Equal
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FCC_UE = 10+16, // Unordered or Equal
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FCC_GE = 11+16, // Greater or Equal
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FCC_UGE = 12+16, // Unordered or Greater or Equal
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FCC_LE = 13+16, // Less or Equal
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FCC_ULE = 14+16, // Unordered or Less or Equal
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FCC_O = 15+16, // Ordered
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CPCC_A = 8+32, // Always
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CPCC_N = 0+32, // Never
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CPCC_3 = 7+32,
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CPCC_2 = 6+32,
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CPCC_23 = 5+32,
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CPCC_1 = 4+32,
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CPCC_13 = 3+32,
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CPCC_12 = 2+32,
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CPCC_123 = 1+32,
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CPCC_0 = 9+32,
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CPCC_03 = 10+32,
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CPCC_02 = 11+32,
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CPCC_023 = 12+32,
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CPCC_01 = 13+32,
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CPCC_013 = 14+32,
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CPCC_012 = 15+32
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};
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}
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inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
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switch (CC) {
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case SPCC::ICC_A: return "a";
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case SPCC::ICC_N: return "n";
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case SPCC::ICC_NE: return "ne";
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case SPCC::ICC_E: return "e";
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case SPCC::ICC_G: return "g";
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case SPCC::ICC_LE: return "le";
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case SPCC::ICC_GE: return "ge";
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case SPCC::ICC_L: return "l";
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case SPCC::ICC_GU: return "gu";
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case SPCC::ICC_LEU: return "leu";
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case SPCC::ICC_CC: return "cc";
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case SPCC::ICC_CS: return "cs";
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case SPCC::ICC_POS: return "pos";
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case SPCC::ICC_NEG: return "neg";
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case SPCC::ICC_VC: return "vc";
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case SPCC::ICC_VS: return "vs";
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case SPCC::FCC_A: return "a";
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case SPCC::FCC_N: return "n";
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case SPCC::FCC_U: return "u";
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case SPCC::FCC_G: return "g";
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case SPCC::FCC_UG: return "ug";
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case SPCC::FCC_L: return "l";
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case SPCC::FCC_UL: return "ul";
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case SPCC::FCC_LG: return "lg";
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case SPCC::FCC_NE: return "ne";
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case SPCC::FCC_E: return "e";
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case SPCC::FCC_UE: return "ue";
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case SPCC::FCC_GE: return "ge";
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case SPCC::FCC_UGE: return "uge";
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case SPCC::FCC_LE: return "le";
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case SPCC::FCC_ULE: return "ule";
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case SPCC::FCC_O: return "o";
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case SPCC::CPCC_A: return "a";
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case SPCC::CPCC_N: return "n";
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case SPCC::CPCC_3: return "3";
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case SPCC::CPCC_2: return "2";
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case SPCC::CPCC_23: return "23";
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case SPCC::CPCC_1: return "1";
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case SPCC::CPCC_13: return "13";
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case SPCC::CPCC_12: return "12";
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case SPCC::CPCC_123: return "123";
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case SPCC::CPCC_0: return "0";
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case SPCC::CPCC_03: return "03";
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case SPCC::CPCC_02: return "02";
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case SPCC::CPCC_023: return "023";
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case SPCC::CPCC_01: return "01";
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case SPCC::CPCC_013: return "013";
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case SPCC::CPCC_012: return "012";
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}
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llvm_unreachable("Invalid cond code");
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}
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inline static unsigned HI22(int64_t imm) {
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return (unsigned)((imm >> 10) & ((1 << 22)-1));
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}
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inline static unsigned LO10(int64_t imm) {
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return (unsigned)(imm & 0x3FF);
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}
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inline static unsigned HIX22(int64_t imm) {
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return HI22(~imm);
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}
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inline static unsigned LOX10(int64_t imm) {
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return ~LO10(~imm);
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}
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} // end namespace llvm
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#endif
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