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ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR instructions to behave the same as LDR/STR with respect to execute-only pages at higher privilege levels. New variants of the MSR/MRS instructions are added to allow reading and writing this bit. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15020 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254157 91177308-0d34-0410-b5e6-96231b3b80d8
20 lines
592 B
Plaintext
20 lines
592 B
Plaintext
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
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[0x7f,0x40,0x00,0xd5]
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[0x7f,0x41,0x00,0xd5]
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[0x7f,0x42,0x00,0xd5]
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# CHECK: msr UAO, #0
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# CHECK: msr UAO, #1
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# CHECK: msr S0_0_C4_C2_3, xzr
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# NO_V82A: msr S0_0_C4_C0_3, xzr
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# NO_V82A: msr S0_0_C4_C1_3, xzr
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# NO_V82A: msr S0_0_C4_C2_3, xzr
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[0x81,0x42,0x18,0xd5]
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[0x82,0x42,0x38,0xd5]
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# CHECK: msr UAO, x1
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# CHECK: mrs x2, UAO
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# NO_V82A: msr S3_0_C4_C2_4, x1
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# NO_V82A: mrs x2, S3_0_C4_C2_4
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