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e927841848
As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275973 91177308-0d34-0410-b5e6-96231b3b80d8
361 lines
12 KiB
LLVM
361 lines
12 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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define <8 x i8> @v_dup8(i8 %A) nounwind {
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;CHECK-LABEL: v_dup8:
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;CHECK: dup.8b
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%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
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%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
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%tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
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%tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3
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%tmp5 = insertelement <8 x i8> %tmp4, i8 %A, i32 4
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%tmp6 = insertelement <8 x i8> %tmp5, i8 %A, i32 5
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%tmp7 = insertelement <8 x i8> %tmp6, i8 %A, i32 6
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%tmp8 = insertelement <8 x i8> %tmp7, i8 %A, i32 7
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ret <8 x i8> %tmp8
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}
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define <4 x i16> @v_dup16(i16 %A) nounwind {
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;CHECK-LABEL: v_dup16:
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;CHECK: dup.4h
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%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
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%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
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%tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
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%tmp4 = insertelement <4 x i16> %tmp3, i16 %A, i32 3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @v_dup32(i32 %A) nounwind {
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;CHECK-LABEL: v_dup32:
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;CHECK: dup.2s
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%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
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%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
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ret <2 x i32> %tmp2
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}
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define <2 x float> @v_dupfloat(float %A) nounwind {
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;CHECK-LABEL: v_dupfloat:
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;CHECK: dup.2s
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%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
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%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
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ret <2 x float> %tmp2
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}
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define <16 x i8> @v_dupQ8(i8 %A) nounwind {
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;CHECK-LABEL: v_dupQ8:
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;CHECK: dup.16b
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%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
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%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
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%tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
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%tmp4 = insertelement <16 x i8> %tmp3, i8 %A, i32 3
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%tmp5 = insertelement <16 x i8> %tmp4, i8 %A, i32 4
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%tmp6 = insertelement <16 x i8> %tmp5, i8 %A, i32 5
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%tmp7 = insertelement <16 x i8> %tmp6, i8 %A, i32 6
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%tmp8 = insertelement <16 x i8> %tmp7, i8 %A, i32 7
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%tmp9 = insertelement <16 x i8> %tmp8, i8 %A, i32 8
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%tmp10 = insertelement <16 x i8> %tmp9, i8 %A, i32 9
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%tmp11 = insertelement <16 x i8> %tmp10, i8 %A, i32 10
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%tmp12 = insertelement <16 x i8> %tmp11, i8 %A, i32 11
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%tmp13 = insertelement <16 x i8> %tmp12, i8 %A, i32 12
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%tmp14 = insertelement <16 x i8> %tmp13, i8 %A, i32 13
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%tmp15 = insertelement <16 x i8> %tmp14, i8 %A, i32 14
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%tmp16 = insertelement <16 x i8> %tmp15, i8 %A, i32 15
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ret <16 x i8> %tmp16
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}
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define <8 x i16> @v_dupQ16(i16 %A) nounwind {
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;CHECK-LABEL: v_dupQ16:
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;CHECK: dup.8h
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%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
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%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
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%tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
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%tmp4 = insertelement <8 x i16> %tmp3, i16 %A, i32 3
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%tmp5 = insertelement <8 x i16> %tmp4, i16 %A, i32 4
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%tmp6 = insertelement <8 x i16> %tmp5, i16 %A, i32 5
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%tmp7 = insertelement <8 x i16> %tmp6, i16 %A, i32 6
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%tmp8 = insertelement <8 x i16> %tmp7, i16 %A, i32 7
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ret <8 x i16> %tmp8
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}
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define <4 x i32> @v_dupQ32(i32 %A) nounwind {
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;CHECK-LABEL: v_dupQ32:
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;CHECK: dup.4s
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%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
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%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
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%tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
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%tmp4 = insertelement <4 x i32> %tmp3, i32 %A, i32 3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @v_dupQfloat(float %A) nounwind {
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;CHECK-LABEL: v_dupQfloat:
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;CHECK: dup.4s
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%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
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%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
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%tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2
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%tmp4 = insertelement <4 x float> %tmp3, float %A, i32 3
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ret <4 x float> %tmp4
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}
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; Check to make sure it works with shuffles, too.
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define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
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;CHECK-LABEL: v_shuffledup8:
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;CHECK: dup.8b
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%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
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;CHECK-LABEL: v_shuffledup16:
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;CHECK: dup.4h
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%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
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;CHECK-LABEL: v_shuffledup32:
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;CHECK: dup.2s
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%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
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ret <2 x i32> %tmp2
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}
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define <2 x float> @v_shuffledupfloat(float %A) nounwind {
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;CHECK-LABEL: v_shuffledupfloat:
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;CHECK: dup.2s
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%tmp1 = insertelement <2 x float> undef, float %A, i32 0
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
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ret <2 x float> %tmp2
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}
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define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ8:
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;CHECK: dup.16b
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%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ16:
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;CHECK: dup.8h
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%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ32:
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;CHECK: dup.4s
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%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %tmp2
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}
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define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
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;CHECK-LABEL: v_shuffledupQfloat:
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;CHECK: dup.4s
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%tmp1 = insertelement <4 x float> undef, float %A, i32 0
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %tmp2
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}
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define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vduplane8:
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;CHECK: dup.8b
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vduplane16:
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;CHECK: dup.4h
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vduplane32:
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;CHECK: dup.2s
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vduplanefloat:
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;CHECK: dup.2s
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ8:
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;CHECK: dup.16b
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ16:
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;CHECK: dup.8h
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ32:
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;CHECK: dup.4s
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vduplaneQfloat:
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;CHECK: dup.4s
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x float> %tmp2
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}
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define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: foo:
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;CHECK: dup.2d
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x i64> %0
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}
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define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: bar:
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;CHECK: dup.2d
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x i64> %0
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}
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define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: baz:
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;CHECK: dup.2d
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %0
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}
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define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
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;CHECK-LABEL: qux:
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;CHECK: dup.2d
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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}
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define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: f:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: ins.s v0[1], w1
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; CHECK-NEXT: ret
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%vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
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%vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
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ret <2 x i32> %vecinit1
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}
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define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: g:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: ins.s v0[1], w1
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; CHECK-NEXT: ins.s v0[2], w1
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; CHECK-NEXT: ins.s v0[3], w0
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; CHECK-NEXT: ret
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%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
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%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
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%vecinit3 = insertelement <4 x i32> %vecinit2, i32 %a, i32 3
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ret <4 x i32> %vecinit3
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}
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define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
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; CHECK-LABEL: h:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: ins.d v0[1], x1
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; CHECK-NEXT: ret
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%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
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%vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
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ret <2 x i64> %vecinit1
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}
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; We used to spot this as a BUILD_VECTOR implementable by dup, but assume that
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; the single value needed was of the same type as the vector. This is false if
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; the scalar corresponding to the vector type is illegal (e.g. a <4 x i16>
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; BUILD_VECTOR will have an i32 as its source). In that case, the operation is
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; not a simple "dup vD.4h, vN.h[idx]" after all, and we crashed.
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;
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; *However*, it is a dup vD.4h, vN.h[2*idx].
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define <4 x i16> @test_build_illegal(<4 x i32> %in) {
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; CHECK-LABEL: test_build_illegal:
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; CHECK: dup.4h v0, v0[6]
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%val = extractelement <4 x i32> %in, i32 3
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%smallval = trunc i32 %val to i16
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%vec = insertelement <4x i16> undef, i16 %smallval, i32 3
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ret <4 x i16> %vec
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}
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; We used to inherit an already extract_subvectored v4i16 from
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; SelectionDAGBuilder here. We then added a DUPLANE on top of that, preventing
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; the formation of an indexed-by-7 MLS.
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define <4 x i16> @test_high_splat(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 {
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; CHECK-LABEL: test_high_splat:
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; CHECK: mls.4h v0, v1, v2[7]
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entry:
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%shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
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%mul = mul <4 x i16> %shuffle, %b
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%sub = sub <4 x i16> %a, %mul
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ret <4 x i16> %sub
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}
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; Also test the DUP path in the PerfectShuffle generator.
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; CHECK-LABEL: test_perfectshuffle_dupext_v4i16:
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; CHECK-NEXT: dup.4h v0, v0[0]
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; CHECK-NEXT: ext.8b v0, v0, v1, #4
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define <4 x i16> @test_perfectshuffle_dupext_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
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%r = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
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ret <4 x i16> %r
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}
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; CHECK-LABEL: test_perfectshuffle_dupext_v4f16:
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; CHECK-NEXT: dup.4h v0, v0[0]
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; CHECK-NEXT: ext.8b v0, v0, v1, #4
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; CHECK-NEXT: ret
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define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b) nounwind {
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%r = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
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ret <4 x half> %r
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}
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; CHECK-LABEL: test_perfectshuffle_dupext_v4i32:
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; CHECK-NEXT: dup.4s v0, v0[0]
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; CHECK-NEXT: ext.16b v0, v0, v1, #8
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; CHECK-NEXT: ret
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define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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|
%r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
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|
ret <4 x i32> %r
|
|
}
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|
|
|
; CHECK-LABEL: test_perfectshuffle_dupext_v4f32:
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|
; CHECK-NEXT: dup.4s v0, v0[0]
|
|
; CHECK-NEXT: ext.16b v0, v0, v1, #8
|
|
; CHECK-NEXT: ret
|
|
define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind {
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|
%r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
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|
ret <4 x float> %r
|
|
}
|