Simon Pilgrim b1ce237a80 [X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239767 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-15 21:49:31 +00:00

..

AArch64

On behalf of Alexandros Lamprineas:

2015-06-15 15:48:44 +00:00

AMDGPU

R600 -> AMDGPU rename

2015-06-13 03:28:10 +00:00

ARM

[ARM] Disabling vfp4 should disable fp16

2015-06-12 09:38:51 +00:00

BPF

[bpf] rename triple names bpf_be -> bpfeb

2015-06-05 16:11:14 +00:00

CPP

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Generic

Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).

2015-05-27 18:02:19 +00:00

Hexagon

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

Inputs

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Mips

[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.

2015-06-02 20:32:50 +00:00

MIR

MIR Serialization: Connect the machine function analysis pass to the MIR parser.

2015-06-15 20:30:22 +00:00

MSP430

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NVPTX

[NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces

2015-06-09 21:50:32 +00:00

PowerPC

LLVM support for vector quad bit permute and gather instructions through builtins

2015-06-11 06:21:25 +00:00

SPARC

Add support for the Sparc implementation-defined "ASR" registers.

2015-05-18 16:29:48 +00:00

SystemZ

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Thumb

Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM."

2015-06-05 18:01:28 +00:00

Thumb2

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

WinEH

[WinEH] C++ EH state numbering fixes

2015-05-20 23:22:24 +00:00

X86

[X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions

2015-06-15 21:49:31 +00:00

XCore

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