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5c562302c2
- Handle simple cases of register copies (what current RDF CP allows). - Hexagon-specific dead code elimination: handles dead address updates in post-increment instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257504 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 -rdf-opt=0 \
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; RUN: < %s | FileCheck %s
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; CHECK: {
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; CHECK: ={{ *}}memd([[REG0:(r[0-9]+)]]{{ *}}++{{ *}}#8)
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; CHECK-NOT: memw([[REG0]]{{ *}}+{{ *}}#0){{ *}}=
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; CHECK: }
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define void @main() #0 {
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cond.end.6:
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store i32 -1, i32* undef, align 8, !tbaa !0
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br label %polly.stmt.for.body.i
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if.then:
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unreachable
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if.end:
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ret void
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polly.stmt.for.body.i24:
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%0 = extractelement <2 x i32> %add.ip_vec, i32 1
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br i1 undef, label %if.end, label %if.then
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polly.stmt.for.body.i:
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%add.ip_vec30 = phi <2 x i32> [ %add.ip_vec, %polly.stmt.for.body.i ], [ zeroinitializer, %cond.end.6 ]
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%scevgep.phi = phi i32* [ %scevgep.inc, %polly.stmt.for.body.i ], [ undef, %cond.end.6 ]
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%polly.indvar = phi i32 [ %polly.indvar_next, %polly.stmt.for.body.i ], [ 0, %cond.end.6 ]
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%vector_ptr = bitcast i32* %scevgep.phi to <2 x i32>*
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%_p_vec_full = load <2 x i32>, <2 x i32>* %vector_ptr, align 8
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%add.ip_vec = add <2 x i32> %_p_vec_full, %add.ip_vec30
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%polly.indvar_next = add nsw i32 %polly.indvar, 2
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%polly.loop_cond = icmp slt i32 %polly.indvar, 4
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%scevgep.inc = getelementptr i32, i32* %scevgep.phi, i32 2
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br i1 %polly.loop_cond, label %polly.stmt.for.body.i, label %polly.stmt.for.body.i24
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}
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attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!0 = !{!"int", !1}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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