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e184e01dd7
The manual is unclear on the details of this. It's not clear to me if denormals are not allowed with clamp, or if that is only omod. Not allowing denorms for fp16 or fp64 isn't useful so I also question if that is really a restriction. Same with whether this is valid without IEEE mode enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295905 91177308-0d34-0410-b5e6-96231b3b80d8
352 lines
10 KiB
TableGen
352 lines
10 KiB
TableGen
//===-- VOPInstructions.td - Vector Instruction Defintions ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// dummies for outer let
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class LetDummies {
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bit isCommutable;
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bit isConvertibleToThreeAddress;
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bit isMoveImm;
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bit isReMaterializable;
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bit isAsCheapAsAMove;
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bit VOPAsmPrefer32Bit;
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Predicate SubtargetPredicate;
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string Constraints;
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string DisableEncoding;
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list<SchedReadWrite> SchedRW;
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list<Register> Uses;
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list<Register> Defs;
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}
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class VOP <string opName> {
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string OpName = opName;
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}
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class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let VALU = 1;
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let Uses = [EXEC];
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}
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class VOP3Common <dag outs, dag ins, string asm = "",
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list<dag> pattern = [], bit HasMods = 0,
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bit VOP3Only = 0> :
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VOPAnyCommon <outs, ins, asm, pattern> {
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// Using complex patterns gives VOP3 patterns a very high complexity rating,
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// but standalone patterns are almost always preferred, so we need to adjust the
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// priority lower. The goal is to use a high number to reduce complexity to
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// zero (or less than zero).
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let AddedComplexity = -1000;
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let VOP3 = 1;
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let AsmMatchConverter =
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!if(!eq(VOP3Only,1),
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"cvtVOP3",
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!if(!eq(HasMods,1), "cvtVOP3_2_mod", ""));
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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let isCodeGenOnly = 0;
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int Size = 8;
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// Because SGPRs may be allowed if there are multiple operands, we
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// need a post-isel hook to insert copies in order to avoid
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// violating constant bus requirements.
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let hasPostISelHook = 1;
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}
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class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP3Only = 0> :
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InstSI <P.Outs64, P.Ins64, "", pattern>,
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VOP <opName>,
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SIMCInstr<opName#"_e64", SIEncodingFamily.NONE>,
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MnemonicAlias<opName#"_e64", opName> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let UseNamedOperandTable = 1;
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string Mnemonic = opName;
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string AsmOperands = P.Asm64;
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let Size = 8;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let SubtargetPredicate = isGCN;
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// Because SGPRs may be allowed if there are multiple operands, we
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// need a post-isel hook to insert copies in order to avoid
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// violating constant bus requirements.
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let hasPostISelHook = 1;
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// Using complex patterns gives VOP3 patterns a very high complexity rating,
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// but standalone patterns are almost always preferred, so we need to adjust the
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// priority lower. The goal is to use a high number to reduce complexity to
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// zero (or less than zero).
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let AddedComplexity = -1000;
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let VOP3 = 1;
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let VALU = 1;
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let FPClamp = P.HasFPClamp;
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let Uses = [EXEC];
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let AsmVariantName = AMDGPUAsmVariants.VOP3;
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let AsmMatchConverter =
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!if(!eq(VOP3Only,1),
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"cvtVOP3",
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!if(!eq(P.HasModifiers, 1), "cvtVOP3_2_mod", ""));
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VOPProfile Pfl = P;
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}
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class VOP3_Real <VOP3_Pseudo ps, int EncodingFamily> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, EncodingFamily> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let AsmVariantName = ps.AsmVariantName;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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}
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class VOP3a<VOPProfile P> : Enc64 {
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<1> clamp;
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bits<2> omod;
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let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
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let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0);
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let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = !if(P.HasSrc0, src0, 0);
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let Inst{49-41} = !if(P.HasSrc1, src1, 0);
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let Inst{58-50} = !if(P.HasSrc2, src2, 0);
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let Inst{60-59} = !if(P.HasOMod, omod, 0);
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let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
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let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
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let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
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}
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class VOP3a_si <bits<9> op, VOPProfile P> : VOP3a<P> {
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let Inst{25-17} = op;
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let Inst{11} = !if(P.HasClamp, clamp{0}, 0);
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}
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class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
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let Inst{25-16} = op;
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let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
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}
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class VOP3e_si <bits<9> op, VOPProfile P> : VOP3a_si <op, P> {
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bits<8> vdst;
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let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
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}
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class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
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bits<8> vdst;
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let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
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}
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class VOP3be <VOPProfile P> : Enc64 {
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bits<8> vdst;
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bits<2> src0_modifiers;
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bits<9> src0;
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bits<2> src1_modifiers;
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bits<9> src1;
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bits<2> src2_modifiers;
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bits<9> src2;
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bits<7> sdst;
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bits<2> omod;
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let Inst{7-0} = vdst;
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let Inst{14-8} = sdst;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = !if(P.HasSrc0, src0, 0);
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let Inst{49-41} = !if(P.HasSrc1, src1, 0);
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let Inst{58-50} = !if(P.HasSrc2, src2, 0);
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let Inst{60-59} = !if(P.HasOMod, omod, 0);
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let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
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let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
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let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
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}
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class VOP3be_si <bits<9> op, VOPProfile P> : VOP3be<P> {
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let Inst{25-17} = op;
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}
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class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> {
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bits<1> clamp;
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let Inst{25-16} = op;
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let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
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}
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def SDWA {
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// sdwa_sel
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int BYTE_0 = 0;
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int BYTE_1 = 1;
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int BYTE_2 = 2;
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int BYTE_3 = 3;
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int WORD_0 = 4;
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int WORD_1 = 5;
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int DWORD = 6;
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// dst_unused
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int UNUSED_PAD = 0;
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int UNUSED_SEXT = 1;
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int UNUSED_PRESERVE = 2;
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}
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class VOP_SDWAe<VOPProfile P> : Enc64 {
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bits<8> src0;
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bits<3> src0_sel;
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bits<2> src0_modifiers; // float: {abs,neg}, int {sext}
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bits<3> src1_sel;
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bits<2> src1_modifiers;
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bits<3> dst_sel;
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bits<2> dst_unused;
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bits<1> clamp;
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let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
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let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, SDWA.DWORD);
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let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, SDWA.UNUSED_PRESERVE);
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let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
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let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, SDWA.DWORD);
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let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
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let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
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let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, SDWA.DWORD);
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let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
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let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0);
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}
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class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
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InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>,
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VOP <opName>,
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SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE>,
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MnemonicAlias <opName#"_sdwa", opName> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let UseNamedOperandTable = 1;
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string Mnemonic = opName;
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string AsmOperands = P.AsmSDWA;
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let Size = 8;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let VALU = 1;
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let SDWA = 1;
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let Uses = [EXEC];
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let SubtargetPredicate = HasSDWA;
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let AssemblerPredicate = !if(P.HasExt, HasSDWA, DisableInst);
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let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.SDWA,
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AMDGPUAsmVariants.Disable);
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let DecoderNamespace = "SDWA";
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VOPProfile Pfl = P;
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}
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class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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let Defs = ps.Defs;
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let Uses = ps.Uses;
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let SchedRW = ps.SchedRW;
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let hasSideEffects = ps.hasSideEffects;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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// Copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AssemblerPredicate = ps.AssemblerPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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let AsmVariantName = ps.AsmVariantName;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let DecoderNamespace = ps.DecoderNamespace;
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let Constraints = ps.Constraints;
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let DisableEncoding = ps.DisableEncoding;
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let TSFlags = ps.TSFlags;
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}
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class VOP_DPPe<VOPProfile P> : Enc64 {
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bits<2> src0_modifiers;
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bits<8> src0;
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bits<2> src1_modifiers;
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bits<9> dpp_ctrl;
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bits<1> bound_ctrl;
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bits<4> bank_mask;
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bits<4> row_mask;
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let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
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let Inst{48-40} = dpp_ctrl;
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let Inst{51} = bound_ctrl;
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let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
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let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
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let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
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let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
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let Inst{59-56} = bank_mask;
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let Inst{63-60} = row_mask;
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}
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class VOP_DPP <string OpName, VOPProfile P> :
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InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, []>,
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VOP_DPPe<P> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let VALU = 1;
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let DPP = 1;
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let Size = 8;
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let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
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let SubtargetPredicate = HasDPP;
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let AssemblerPredicate = !if(P.HasExt, HasDPP, DisableInst);
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let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
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AMDGPUAsmVariants.Disable);
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let DecoderNamespace = "DPP";
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}
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include "VOPCInstructions.td"
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include "VOP1Instructions.td"
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include "VOP2Instructions.td"
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include "VOP3Instructions.td"
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