mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-03 09:21:13 +00:00
41cf463348
GCC 4.7's libstdc++ doesn't have std::map::emplace, but it does have std::unordered_map::emplace, and the use case here doesn't appear to need ordering. The container has been changed in a separate/precursor patch, and now this patch should hopefully build cleanly even with GCC 4.7. & then I realized the order of the container did matter, so extra handling of ordering was added in r231189. Original commit message: This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231192 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
3.0 KiB
C++
91 lines
3.0 KiB
C++
//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements the live stack slot analysis pass. It is analogous to
|
|
// live interval analysis except it's analyzing liveness of stack slots rather
|
|
// than registers.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/CodeGen/LiveStackAnalysis.h"
|
|
#include "llvm/ADT/Statistic.h"
|
|
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
|
#include "llvm/CodeGen/Passes.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
#include "llvm/Target/TargetSubtargetInfo.h"
|
|
#include <limits>
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "livestacks"
|
|
|
|
char LiveStacks::ID = 0;
|
|
INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
|
|
"Live Stack Slot Analysis", false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
|
|
INITIALIZE_PASS_END(LiveStacks, "livestacks",
|
|
"Live Stack Slot Analysis", false, false)
|
|
|
|
char &llvm::LiveStacksID = LiveStacks::ID;
|
|
|
|
void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesAll();
|
|
AU.addPreserved<SlotIndexes>();
|
|
AU.addRequiredTransitive<SlotIndexes>();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
void LiveStacks::releaseMemory() {
|
|
// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
|
|
VNInfoAllocator.Reset();
|
|
S2IMap.clear();
|
|
S2RCMap.clear();
|
|
}
|
|
|
|
bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
|
// FIXME: No analysis is being done right now. We are relying on the
|
|
// register allocators to provide the information.
|
|
return false;
|
|
}
|
|
|
|
LiveInterval &
|
|
LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
|
|
assert(Slot >= 0 && "Spill slot indice must be >= 0");
|
|
SS2IntervalMap::iterator I = S2IMap.find(Slot);
|
|
if (I == S2IMap.end()) {
|
|
I = S2IMap.emplace(std::piecewise_construct, std::forward_as_tuple(Slot),
|
|
std::forward_as_tuple(
|
|
TargetRegisterInfo::index2StackSlot(Slot), 0.0F))
|
|
.first;
|
|
S2RCMap.insert(std::make_pair(Slot, RC));
|
|
} else {
|
|
// Use the largest common subclass register class.
|
|
const TargetRegisterClass *OldRC = S2RCMap[Slot];
|
|
S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
|
|
}
|
|
return I->second;
|
|
}
|
|
|
|
/// print - Implement the dump method.
|
|
void LiveStacks::print(raw_ostream &OS, const Module*) const {
|
|
|
|
OS << "********** INTERVALS **********\n";
|
|
for (const_iterator I = begin(), E = end(); I != E; ++I) {
|
|
I->second.print(OS);
|
|
int Slot = I->first;
|
|
const TargetRegisterClass *RC = getIntervalRegClass(Slot);
|
|
if (RC)
|
|
OS << " [" << TRI->getRegClassName(RC) << "]\n";
|
|
else
|
|
OS << " [Unknown]\n";
|
|
}
|
|
}
|