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6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
2.7 KiB
LLVM
113 lines
2.7 KiB
LLVM
; Test 64-bit atomic additions.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Check addition of a variable.
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define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: lgr %r0, %r2
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; CHECK: agr %r0, %r4
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; CHECK: csg %r2, %r0, 0(%r3)
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; CHECK: jl [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 %b seq_cst
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ret i64 %res
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}
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; Check addition of 1, which can use AGHI.
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define i64 @f2(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lg %r2, 0(%r3)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: lgr %r0, %r2
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; CHECK: aghi %r0, 1
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; CHECK: csg %r2, %r0, 0(%r3)
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; CHECK: jl [[LABEL]]
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 1 seq_cst
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ret i64 %res
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}
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; Check the high end of the AGHI range.
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define i64 @f3(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: aghi %r0, 32767
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 32767 seq_cst
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ret i64 %res
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}
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; Check the next value up, which must use AGFI.
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define i64 @f4(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r0, 32768
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 32768 seq_cst
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ret i64 %res
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}
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; Check the high end of the AGFI range.
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define i64 @f5(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: agfi %r0, 2147483647
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 2147483647 seq_cst
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ret i64 %res
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}
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; Check the next value up, which must use a register addition.
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define i64 @f6(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: agr
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 2147483648 seq_cst
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ret i64 %res
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}
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; Check addition of -1, which can use AGHI.
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define i64 @f7(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: aghi %r0, -1
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 -1 seq_cst
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ret i64 %res
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}
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; Check the low end of the AGHI range.
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define i64 @f8(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: aghi %r0, -32768
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 -32768 seq_cst
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ret i64 %res
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}
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; Check the next value down, which must use AGFI instead.
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define i64 @f9(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r0, -32769
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 -32769 seq_cst
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ret i64 %res
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}
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; Check the low end of the AGFI range.
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define i64 @f10(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r0, -2147483648
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst
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ret i64 %res
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}
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; Check the next value down, which must use a register addition.
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define i64 @f11(i64 %dummy, i64 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: agr
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; CHECK: br %r14
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%res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst
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ret i64 %res
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}
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