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7e0334d096
When lowering a load or store for TypeWidenVector, the type legalizer would use a single load or store if the associated integer type was legal. E.g. it would load a v4i8 as an i32 if i32 was legal. This patch extends that behavior to promoted integers as well as legal ones. If the integer type for the full vector width is TypePromoteInteger, the element type is going to be TypePromoteInteger too, and it's still better to use a single promoting load or truncating store rather than N individual promoting loads or truncating stores. E.g. if you have a v2i8 on a target where i16 is promoted to i32, it's better to load the v2i8 as an i16 rather than load both i8s individually. Original patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236528 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
2.8 KiB
LLVM
106 lines
2.8 KiB
LLVM
; Test vector zero-extending loads.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i1->v16i8 extension.
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define <16 x i8> @f1(<16 x i1> *%ptr) {
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; No expected output, but must compile.
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%val = load <16 x i1>, <16 x i1> *%ptr
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%ret = zext <16 x i1> %val to <16 x i8>
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ret <16 x i8> %ret
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}
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; Test a v8i1->v8i16 extension.
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define <8 x i16> @f2(<8 x i1> *%ptr) {
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; No expected output, but must compile.
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%val = load <8 x i1>, <8 x i1> *%ptr
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%ret = zext <8 x i1> %val to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test a v8i8->v8i16 extension.
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define <8 x i16> @f3(<8 x i8> *%ptr) {
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; CHECK-LABEL: f3:
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; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK: vuplhb %v24, [[REG1]]
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; CHECK: br %r14
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%val = load <8 x i8>, <8 x i8> *%ptr
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%ret = zext <8 x i8> %val to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test a v4i1->v4i32 extension.
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define <4 x i32> @f4(<4 x i1> *%ptr) {
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; No expected output, but must compile.
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%val = load <4 x i1>, <4 x i1> *%ptr
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%ret = zext <4 x i1> %val to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v4i8->v4i32 extension.
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define <4 x i32> @f5(<4 x i8> *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
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; CHECK: vuplhh %v24, [[REG2]]
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; CHECK: br %r14
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%val = load <4 x i8>, <4 x i8> *%ptr
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%ret = zext <4 x i8> %val to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v4i16->v4i32 extension.
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define <4 x i32> @f6(<4 x i16> *%ptr) {
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; CHECK-LABEL: f6:
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; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK: vuplhh %v24, [[REG1]]
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; CHECK: br %r14
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%val = load <4 x i16>, <4 x i16> *%ptr
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%ret = zext <4 x i16> %val to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v2i1->v2i64 extension.
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define <2 x i64> @f7(<2 x i1> *%ptr) {
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; No expected output, but must compile.
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%val = load <2 x i1>, <2 x i1> *%ptr
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%ret = zext <2 x i1> %val to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i8->v2i64 extension.
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define <2 x i64> @f8(<2 x i8> *%ptr) {
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; CHECK-LABEL: f8:
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; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
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; CHECK: vuplhh [[REG3:%v[0-9]+]], [[REG2]]
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; CHECK: vuplhf %v24, [[REG3]]
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; CHECK: br %r14
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%val = load <2 x i8>, <2 x i8> *%ptr
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%ret = zext <2 x i8> %val to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i16->v2i64 extension.
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define <2 x i64> @f9(<2 x i16> *%ptr) {
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; CHECK-LABEL: f9:
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; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK: vuplhh [[REG2:%v[0-9]+]], [[REG1]]
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; CHECK: vuplhf %v24, [[REG2]]
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; CHECK: br %r14
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%val = load <2 x i16>, <2 x i16> *%ptr
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%ret = zext <2 x i16> %val to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i32->v2i64 extension.
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define <2 x i64> @f10(<2 x i32> *%ptr) {
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; CHECK-LABEL: f10:
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; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
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; CHECK: vuplhf %v24, [[REG1]]
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; CHECK: br %r14
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%val = load <2 x i32>, <2 x i32> *%ptr
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%ret = zext <2 x i32> %val to <2 x i64>
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ret <2 x i64> %ret
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}
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