mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-04 01:43:06 +00:00
d1e8d9c0a5
- Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.5 KiB
TableGen
42 lines
1.5 KiB
TableGen
//===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===//
|
|
//
|
|
// Cell SPU 128-bit operations
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// zext 32->128: Zero extend 32-bit to 128-bit
|
|
def : Pat<(i128 (zext R32C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
|
|
|
|
// zext 64->128: Zero extend 64-bit to 128-bit
|
|
def : Pat<(i128 (zext R64C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r64 R64C:$rSrc, 8)>;
|
|
|
|
// zext 16->128: Zero extend 16-bit to 128-bit
|
|
def : Pat<(i128 (zext R16C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r32 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff)), 12)>;
|
|
|
|
// zext 8->128: Zero extend 8-bit to 128-bit
|
|
def : Pat<(i128 (zext R8C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r32 (ANDIi8i32 R8C:$rSrc, 0xf), 12)>;
|
|
|
|
// anyext 32->128: Zero extend 32-bit to 128-bit
|
|
def : Pat<(i128 (anyext R32C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
|
|
|
|
// anyext 64->128: Zero extend 64-bit to 128-bit
|
|
def : Pat<(i128 (anyext R64C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r64 R64C:$rSrc, 8)>;
|
|
|
|
// anyext 16->128: Zero extend 16-bit to 128-bit
|
|
def : Pat<(i128 (anyext R16C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r32 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff)), 12)>;
|
|
|
|
// anyext 8->128: Zero extend 8-bit to 128-bit
|
|
def : Pat<(i128 (anyext R8C:$rSrc)),
|
|
(ROTQMBYIr128_zext_r32 (ANDIi8i32 R8C:$rSrc, 0xf), 12)>;
|
|
|
|
// Shift left
|
|
def : Pat<(shl GPRC:$rA, R32C:$rB),
|
|
(SHLQBYBIr128 (SHLQBIr128 GPRC:$rA, R32C:$rB), R32C:$rB)>;
|