llvm/unittests/Support/Host.cpp
Yi Kong 4dd33e6269 Implement host CPU detection for AArch64
This shares detection logic with ARM(32), since AArch64 capable CPUs may
also run in 32-bit system mode.

We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where
they report all CPU cores as one single model, depending on which CPU
core the kernel is running on. As a workaround, we hardcode the known
CPU part name for these SoCs.

For big.LITTLE systems, this patch would only return the part name of
the first core (usually the little core). Proper support will be added
in a follow-up change.

Differential Revision: D31675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299458 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:06:04 +00:00

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3.6 KiB
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//========- unittests/Support/Host.cpp - Host.cpp tests --------------========//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "llvm/Support/Host.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Triple.h"
#include "gtest/gtest.h"
using namespace llvm;
class HostTest : public testing::Test {
Triple Host;
protected:
bool isSupportedArchAndOS() {
// Initially this is only testing detection of the number of
// physical cores, which is currently only supported/tested for
// x86_64 Linux and Darwin.
return (Host.getArch() == Triple::x86_64 &&
(Host.isOSDarwin() || Host.getOS() == Triple::Linux));
}
HostTest() : Host(Triple::normalize(sys::getProcessTriple())) {}
};
TEST_F(HostTest, NumPhysicalCores) {
int Num = sys::getHostNumPhysicalCores();
if (isSupportedArchAndOS())
ASSERT_GT(Num, 0);
else
ASSERT_EQ(Num, -1);
}
TEST(getLinuxHostCPUName, ARM) {
StringRef CortexA9ProcCpuinfo = R"(
processor : 0
model name : ARMv7 Processor rev 10 (v7l)
BogoMIPS : 1393.66
Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc09
CPU revision : 10
processor : 1
model name : ARMv7 Processor rev 10 (v7l)
BogoMIPS : 1393.66
Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x2
CPU part : 0xc09
CPU revision : 10
Hardware : Generic OMAP4 (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
)";
EXPECT_EQ(sys::detail::getHostCPUNameForARM(CortexA9ProcCpuinfo),
"cortex-a9");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
"CPU part : 0xc0f"),
"cortex-a15");
// Verify that both CPU implementer and CPU part are checked:
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
"CPU part : 0xc0f"),
"generic");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
"CPU part : 0x06f"),
"krait");
}
TEST(getLinuxHostCPUName, AArch64) {
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
"CPU part : 0xd03"),
"cortex-a53");
// Verify that both CPU implementer and CPU part are checked:
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
"CPU part : 0xd03"),
"generic");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
"CPU part : 0x201"),
"kryo");
// MSM8992/4 weirdness
StringRef MSM8992ProcCpuInfo = R"(
Processor : AArch64 Processor rev 3 (aarch64)
processor : 0
processor : 1
processor : 2
processor : 3
processor : 4
processor : 5
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 3
Hardware : Qualcomm Technologies, Inc MSM8992
)";
EXPECT_EQ(sys::detail::getHostCPUNameForARM(MSM8992ProcCpuInfo),
"cortex-a53");
}