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8f2a85e099
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.0 KiB
LLVM
48 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=ppc64 | FileCheck %s
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define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange_and_add:
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; CHECK: ldarx
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%tmp = atomicrmw add i64* %mem, i64 %val monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i64 @exchange_and_cmp(i64* %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp:
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; CHECK: ldarx
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%tmppair = cmpxchg i64* %mem, i64 0, i64 1 monotonic monotonic
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%tmp = extractvalue { i64, i1 } %tmppair, 0
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; CHECK: stdcx.
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i64 @exchange(i64* %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange:
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; CHECK: ldarx
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%tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define void @atomic_store(i64* %mem, i64 %val) nounwind {
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entry:
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; CHECK: @atomic_store
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store atomic i64 %val, i64* %mem release, align 64
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; CHECK: ldarx
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; CHECK: stdcx.
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ret void
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}
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define i64 @atomic_load(i64* %mem) nounwind {
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entry:
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; CHECK: @atomic_load
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%tmp = load atomic i64* %mem acquire, align 64
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; CHECK: ldarx
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; CHECK: stdcx.
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; CHECK: stdcx.
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ret i64 %tmp
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}
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