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https://github.com/RPCSX/llvm.git
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c146d1a1e5
Added support to map intrinsics
__builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l}
to their ARM instructions.
Differential Revision: http://reviews.llvm.org/D20564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271271 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.9 KiB
LLVM
72 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
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define void @coproc(i8* %i) nounwind {
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entry:
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; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
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%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
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; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: cdp p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: cdp2 p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: ldc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
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ret void
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}
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declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc(i32, i32, i8*) nounwind
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declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
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