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cead1b4a6d
Summary: It is off by default, but can be used with --misched=si Patch by: Axel Davy Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: nhaehnle, solenskiner, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D11885 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257609 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
2.4 KiB
LLVM
56 lines
2.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI --misched=si < %s | FileCheck %s
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; The test checks the "si" machine scheduler pass works correctly.
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; CHECK-LABEL: {{^}}main:
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; CHECK: s_wqm
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; CHECK: s_load_dwordx4
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; CHECK: s_load_dwordx8
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; CHECK: s_waitcnt lgkmcnt(0)
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; CHECK: image_sample
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; CHECK: s_waitcnt vmcnt(0)
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; CHECK: exp
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; CHECK: s_endpgm
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define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>,
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<2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
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main_body:
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%22 = bitcast [34 x <8 x i32>] addrspace(2)* %3 to <32 x i8> addrspace(2)*
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%23 = load <32 x i8>, <32 x i8> addrspace(2)* %22, align 32, !tbaa !0
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%24 = bitcast [17 x <4 x i32>] addrspace(2)* %2 to <16 x i8> addrspace(2)*
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%25 = load <16 x i8>, <16 x i8> addrspace(2)* %24, align 16, !tbaa !0
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%26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11)
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%27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11)
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%28 = bitcast float %26 to i32
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%29 = bitcast float %27 to i32
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%30 = insertelement <2 x i32> undef, i32 %28, i32 0
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%31 = insertelement <2 x i32> %30, i32 %29, i32 1
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%32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 2)
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%33 = extractelement <4 x float> %32, i32 0
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%34 = extractelement <4 x float> %32, i32 1
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%35 = extractelement <4 x float> %32, i32 2
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%36 = extractelement <4 x float> %32, i32 3
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%37 = call i32 @llvm.SI.packf16(float %33, float %34)
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%38 = bitcast i32 %37 to float
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%39 = call i32 @llvm.SI.packf16(float %35, float %36)
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%40 = bitcast i32 %39 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
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attributes #1 = { nounwind readnone }
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!0 = !{!"const", null, i32 1}
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