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567409db69
This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274189 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
4.9 KiB
C++
120 lines
4.9 KiB
C++
//===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
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#include "MipsInstrInfo.h"
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#include "MipsSERegisterInfo.h"
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namespace llvm {
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class MipsSEInstrInfo : public MipsInstrInfo {
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const MipsSERegisterInfo RI;
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public:
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explicit MipsSEInstrInfo(const MipsSubtarget &STI);
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const MipsRegisterInfo &getRegisterInfo() const override;
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const override;
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void loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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unsigned getOppositeBranchOpc(unsigned Opc) const override;
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/// Adjust SP by Amount bytes.
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void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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/// Emit a series of instructions to load an immediate. If NewImm is a
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/// non-NULL parameter, the last instruction is not emitted, but instead
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/// its immediate operand is returned in NewImm.
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unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, const DebugLoc &DL,
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unsigned *NewImm) const;
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private:
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unsigned getAnalyzableBrOpc(unsigned Opc) const override;
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void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
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void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
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std::pair<bool, bool> compareOpndSize(unsigned Opc,
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const MachineFunction &MF) const;
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void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned NewOpc) const;
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void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned LoOpc, unsigned HiOpc,
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bool HasExplicitDef) const;
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/// Expand pseudo Int-to-FP conversion instructions.
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///
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/// For example, the following pseudo instruction
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/// PseudoCVT_D32_W D2, A5
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/// gets expanded into these two instructions:
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/// MTC1 F4, A5
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/// CVT_D32_W D2, F4
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///
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/// We do this expansion post-RA to avoid inserting a floating point copy
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/// instruction between MTC1 and CVT_D32_W.
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void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
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void expandExtractElementF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandBuildPairF64(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, bool FP64) const;
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void expandEhReturn(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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};
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}
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#endif
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