llvm/test/CodeGen
Arnold Schwaighofer c46e2df74c DAGCombiner: Fold pointless truncate, bitcast, buildvector series
(2xi32) (truncate ((2xi64) bitcast (buildvector i32 a, i32 x, i32 b, i32 y)))
can be folded into a (2xi32) (buildvector i32 a, i32 b).

Such a DAG would cause uneccessary vdup instructions followed by vmovn
instructions.

We generate this code on ARM NEON for a setcc olt, 2xf64, 2xf64. For example, in
the vectorized version of the code below.

double A[N];
double B[N];

void test_double_compare_to_double() {
  int i;
  for(i=0;i<N;i++)
    A[i] = (double)(A[i] < B[i]);
}

radar://13191881

Fixes bug 15283.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175670 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 21:33:32 +00:00
..
AArch64 AArch64: remove ConstantIsland pass & put literals in separate section. 2013-02-15 09:33:43 +00:00
ARM DAGCombiner: Fold pointless truncate, bitcast, buildvector series 2013-02-20 21:33:32 +00:00
CPP
Generic For inline asm: 2013-01-11 18:12:39 +00:00
Hexagon Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. 2013-02-20 16:13:27 +00:00
MBlaze
Mips Expand pseudos/macros: 2013-02-20 05:45:15 +00:00
MSP430 Add support for varargs functions for msp430. 2012-11-21 17:28:27 +00:00
NVPTX [NVPTX] Disable vector registers 2013-02-12 14:18:49 +00:00
PowerPC Additional fixes for bug 15155. 2013-02-20 20:41:42 +00:00
R600 R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern 2013-02-18 14:11:28 +00:00
SI Add R600 backend 2012-12-11 21:25:42 +00:00
SPARC Use TargetTransformInfo to control switch-to-lookup table transformation 2012-10-30 11:23:25 +00:00
Thumb Fix thumbv5e frame lowering assertion failure. 2013-02-20 12:21:33 +00:00
Thumb2 ARM: Allocation hints must make sure to be in the alloc order. 2013-02-19 18:55:36 +00:00
X86 Fix PR15267 2013-02-20 18:04:21 +00:00
XCore Fix handling of aliases to functions. 2012-11-16 21:12:38 +00:00