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c5b4632c27
(1) Ensure that delay slot instructions are not moved out of place (this was happening for some CALL instructions). Basically, we need to move all delay slot instructions out of the graph and handle them along with the delayed control transfer instruction. (2) Mark scheduled instructions correctly when instructions are scheduled in more than one cycle in a single step (due to delay slots). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@678 91177308-0d34-0410-b5e6-96231b3b80d8 |
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SparcV9 | ||
Makefile | ||
TargetData.cpp | ||
TargetMachine.cpp | ||
TargetSchedInfo.cpp |