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https://github.com/RPCSX/llvm.git
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d2c33c4ecb
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287162 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
2.2 KiB
LLVM
57 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=avr | FileCheck %s
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; XFAIL: *
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; This occurs when compiling Rust libcore.
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;
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; Assertion failed:
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; (DstReg != SrcReg && "SrcReg and DstReg cannot be the same")
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; lib/Target/AVR/AVRExpandPseudoInsts.cpp, line 817
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;
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; https://github.com/avr-llvm/llvm/issues/229
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; CHECK-LABEL: rust_eh_personality
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declare void @rust_eh_personality()
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; CHECK-LABEL: __udivmoddi4
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define void @__udivmoddi4(i64 %arg, i64 %arg1) personality i32 (...)* bitcast (void ()* @rust_eh_personality to i32 (...)*) {
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entry-block:
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%tmp = lshr i64 %arg, 32
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%tmp2 = trunc i64 %tmp to i32
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%tmp3 = trunc i64 %arg to i32
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%tmp4 = add i64 %arg1, -1
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br label %bb135
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bb133.loopexit:
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ret void
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bb135:
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%carry.0120 = phi i64 [ 0, %entry-block ], [ %phitmp, %bb135 ]
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%q.sroa.12.1119 = phi i32 [ %tmp3, %entry-block ], [ %q.sroa.12.0.extract.trunc, %bb135 ]
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%q.sroa.0.1118 = phi i32 [ 0, %entry-block ], [ %q.sroa.0.0.extract.trunc, %bb135 ]
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%r.sroa.0.1116 = phi i32 [ %tmp2, %entry-block ], [ undef, %bb135 ]
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%r.sroa.0.0.insert.ext62 = zext i32 %r.sroa.0.1116 to i64
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%r.sroa.0.0.insert.insert64 = or i64 0, %r.sroa.0.0.insert.ext62
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%tmp5 = shl nuw nsw i64 %r.sroa.0.0.insert.ext62, 1
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%q.sroa.12.0.insert.ext101 = zext i32 %q.sroa.12.1119 to i64
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%q.sroa.12.0.insert.shift102 = shl nuw i64 %q.sroa.12.0.insert.ext101, 32
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%q.sroa.0.0.insert.ext87 = zext i32 %q.sroa.0.1118 to i64
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%q.sroa.0.0.insert.insert89 = or i64 %q.sroa.12.0.insert.shift102, %q.sroa.0.0.insert.ext87
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%tmp6 = lshr i64 %q.sroa.12.0.insert.ext101, 31
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%tmp7 = lshr i64 %r.sroa.0.0.insert.insert64, 31
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%tmp8 = shl nuw nsw i64 %q.sroa.0.0.insert.ext87, 1
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%tmp9 = or i64 %tmp8, %carry.0120
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%q.sroa.0.0.extract.trunc = trunc i64 %tmp9 to i32
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%tmp10 = lshr i64 %q.sroa.0.0.insert.insert89, 31
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%q.sroa.12.0.extract.trunc = trunc i64 %tmp10 to i32
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%r.sroa.13.0.insert.shift72 = shl i64 %tmp7, 32
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%.masked114 = and i64 %tmp5, 4294967294
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%r.sroa.0.0.insert.ext57 = or i64 %tmp6, %.masked114
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%r.sroa.0.0.insert.insert59 = or i64 %r.sroa.0.0.insert.ext57, %r.sroa.13.0.insert.shift72
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%tmp11 = sub i64 %tmp4, %r.sroa.0.0.insert.insert59
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%tmp12 = ashr i64 %tmp11, 63
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%phitmp = and i64 %tmp12, 1
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%tmp13 = icmp ult i32 undef, 32
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br i1 %tmp13, label %bb135, label %bb133.loopexit
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}
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