Sanjay Patel c826b54b52 [x86] Add a reassociation optimization to increase ILP via the MachineCombiner pass ...

This is a reimplementation of D9780 at the machine instruction level rather than the DAG.

Use the MachineCombiner pass to reassociate scalar single-precision AVX additions (just a
starting point; see the TODO comments) to increase ILP when it's safe to do so.

The code is closely based on the existing MachineCombiner optimization that is implemented
for AArch64.

This patch should not cause the kind of spilling tragedy that led to the reversion of r236031.

Differential Revision: http://reviews.llvm.org/D10321



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239486 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-10 20:32:21 +00:00

..

AArch64

[AArch64] Remove an overly conservative check when generating store pairs.

2015-06-09 20:59:41 +00:00

ARM

Add explicit -mtriple=arm-unknown to llvm/test/CodeGen/ARM/disable-tail-calls.ll, to satisfy *-win32.

2015-06-09 23:33:25 +00:00

BPF

[bpf] rename triple names bpf_be -> bpfeb

2015-06-05 16:11:14 +00:00

CPP

[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction

2015-04-16 23:24:18 +00:00

Generic

Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).

2015-05-27 18:02:19 +00:00

Hexagon

[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.

2015-06-10 16:52:32 +00:00

Inputs

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

Mips

[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.

2015-06-02 20:32:50 +00:00

MIR

MIR Serialization: use correct line and column numbers for LLVM IR errors.

2015-05-29 17:05:41 +00:00

MSP430

[opaque pointer type] Add textual IR support for explicit type parameter to gep operator

2015-03-13 18:20:45 +00:00

NVPTX

[NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces

2015-06-09 21:50:32 +00:00

PowerPC

Add support for VSX FMA single-precision instructions to the PPC back end

2015-05-29 17:13:25 +00:00

R600

Implement computeKnownBits for min/max nodes

2015-06-09 00:52:41 +00:00

SPARC

Add support for the Sparc implementation-defined "ASR" registers.

2015-05-18 16:29:48 +00:00

SystemZ

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

2015-05-05 19:34:10 +00:00

Thumb

Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM."

2015-06-05 18:01:28 +00:00

Thumb2

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

WinEH

[WinEH] C++ EH state numbering fixes

2015-05-20 23:22:24 +00:00

X86

[x86] Add a reassociation optimization to increase ILP via the MachineCombiner pass

2015-06-10 20:32:21 +00:00

XCore

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00