llvm/test/CodeGen/NVPTX/intrinsics.ll
Justin Holewinski 7e6565112b [NVPTX] Rename registers %fl -> %fd and %rl -> %rd
This matches the internal behavior of NVIDIA tools like libnvvm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213168 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-16 16:26:58 +00:00

27 lines
676 B
LLVM

; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
define ptx_device float @test_fabsf(float %f) {
; CHECK: abs.f32 %f{{[0-9]+}}, %f{{[0-9]+}};
; CHECK: ret;
%x = call float @llvm.fabs.f32(float %f)
ret float %x
}
define ptx_device double @test_fabs(double %d) {
; CHECK: abs.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}};
; CHECK: ret;
%x = call double @llvm.fabs.f64(double %d)
ret double %x
}
define float @test_nvvm_sqrt(float %a) {
%val = call float @llvm.nvvm.sqrt.f(float %a)
ret float %val
}
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
declare float @llvm.nvvm.sqrt.f(float)