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5fe5b3dcc8
More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
2.5 KiB
LLVM
117 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 -show-mc-encoding %s -o - \
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; RUN: | FileCheck %s
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define i32 @f1(i32 %a.s) {
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entry:
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; CHECK-LABEL: f1:
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; CHECK: it eq
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; CHECK: moveq
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%tmp = icmp eq i32 %a.s, 4
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f2(i32 %a.s) {
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entry:
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; CHECK-LABEL: f2:
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; CHECK: it gt
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; CHECK: movgt
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%tmp = icmp sgt i32 %a.s, 4
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f3(i32 %a.s, i32 %b.s) {
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entry:
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; CHECK-LABEL: f3:
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; CHECK: it lt
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; CHECK: movlt
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%tmp = icmp slt i32 %a.s, %b.s
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f4(i32 %a.s, i32 %b.s) {
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entry:
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; CHECK-LABEL: f4:
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; CHECK: it le
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; CHECK: movle
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%tmp = icmp sle i32 %a.s, %b.s
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f5(i32 %a.u, i32 %b.u) {
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entry:
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; CHECK-LABEL: f5:
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; CHECK: it ls
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; CHECK: movls
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%tmp = icmp ule i32 %a.u, %b.u
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f6(i32 %a.u, i32 %b.u) {
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entry:
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; CHECK-LABEL: f6:
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; CHECK: it hi
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; CHECK: movhi
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%tmp = icmp ugt i32 %a.u, %b.u
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%tmp1.s = select i1 %tmp, i32 2, i32 3
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ret i32 %tmp1.s
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}
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define i32 @f7(i32 %a, i32 %b, i32 %c) {
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entry:
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; CHECK-LABEL: f7:
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; CHECK: it hi
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; CHECK: lsrhi {{r[0-9]+}}
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%tmp1 = icmp ugt i32 %a, %b
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%tmp2 = udiv i32 %c, 3
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%tmp3 = select i1 %tmp1, i32 %tmp2, i32 3
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ret i32 %tmp3
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}
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define i32 @f8(i32 %a, i32 %b, i32 %c) {
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entry:
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; CHECK-LABEL: f8:
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; CHECK: it lo
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; CHECK: lsllo {{r[0-9]+}}
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%tmp1 = icmp ult i32 %a, %b
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%tmp2 = mul i32 %c, 4
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%tmp3 = select i1 %tmp1, i32 %tmp2, i32 3
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ret i32 %tmp3
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}
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define i32 @f9(i32 %a, i32 %b, i32 %c) {
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entry:
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; CHECK-LABEL: f9:
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; CHECK: it ge
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; CHECK: rorge.w
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%tmp1 = icmp sge i32 %a, %b
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%tmp2 = shl i32 %c, 10
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%tmp3 = lshr i32 %c, 22
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = select i1 %tmp1, i32 %tmp4, i32 3
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ret i32 %tmp5
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}
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: movwne {{r[0-9]+}}, #1234 @ encoding: [0x40,0xf2,0xd2,0x4{{[0-9a-f]+}}]
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%tst = icmp ne i32 %a, %b
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%val = select i1 %tst, i32 1234, i32 12345
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ret i32 %val
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}
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; Make sure we pick the Thumb encoding for movw/movt
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define i32 @f11(i32 %a, i32 %b) {
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; CHECK-LABEL: f11:
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; CHECK: movwne {{r[0-9]+}}, #50033 @ encoding: [0x4c,0xf2,0x71,0x3{{[0-9a-f]+}}]
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%tst = icmp ne i32 %a, %b
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%val = select i1 %tst, i32 123454321, i32 543212345
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ret i32 %val
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}
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